XC6VLX130T-1FF484I Datasheet, PDF (39/65 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 51: ISERDES Switching Characteristics
Symbol
Description
-3
Setup/Hold for Control Lines
T_{ISCCK_BITSLIP}/ T_{ISCKC_BITSLIP}
T_{ISCCK_CE} / T_{ISCKC_CE(2)}
T_{ISCCK_CE2} / T_{ISCKC_CE2(2)}
BITSLIP pin Setup/Hold with respect to
CLKDIV
CE pin Setup/Hold with respect to CLK
(for CE1)
CE pin Setup/Hold with respect to CLKDIV
(for CE2)
0.07/
0.15
0.20/
0.03
0.01/
0.27
Setup/Hold for Data Lines
T_{ISDCK_D} /T_{ISCKD_D}
D pin Setup/Hold with respect to CLK
0.07/
0.08
T_{ISDCK_DDLY} /T_{ISCKD_DDLY}
DDLY pin Setup/Hold with respect to CLK
(using IODELAY)⁽¹⁾
0.10/
0.05
T_{ISDCK_D_DDR} /T_{ISCKD_D_DDR} D pin Setup/Hold with respect to CLK at
DDR mode
0.07/
0.08
T_{ISDCK_DDLY_DDR}
T_{ISCKD_DDLY_DDR}
Sequential Delays
D pin Setup/Hold with respect to CLK at
DDR mode (using IODELAY)⁽¹⁾
0.10/
0.05
T_{ISCKO_Q}
Propagation Delays
CLKDIV to out at Q pin
0.57
T_{ISDO_DO}
D input to DO output pin
0.19
Notes:
1. Recorded at 0 tap value.
2. T_{ISCCK_CE2} and T_{ISCKC_CE2} are reported as T_{ISCCK_CE}/T_{ISCKC_CE} in TRACE report.
Speed Grade
Units
-2 -1 (XC) -1 (XQ) -1L
0.08/ 0.09/ 0.09/ 0.14/ ns
0.16 0.17 0.17 0.17
0.25/ 0.27/ 0.27/ 0.31/ ns
0.04 0.04 0.04 0.05
0.01 0.01/ 0.01/ –0.05/ ns
0.29 0.31 0.31 0.35
0.08/ 0.09/ 0.09/ 0.11/ ns
0.09 0.11 0.11 0.19
0.12/ 0.14/ 0.14/ 0.16/ ns
0.06 0.07 0.07 0.15
0.08/ 0.09/ 0.09/ 0.11/ ns
0.09 0.11 0.11 0.19
0.12/ 0.14/ 0.14/ 0.16/ ns
0.06 0.07 0.07 0.15
0.66 0.75 0.80 0.88 ns
0.22 0.25 0.25 0.28 ns
DS152 (v3.5) May 17, 2013
www.xilinx.com
Product Specification
39