XC6VLX130T-1FF484I Datasheet, PDF (38/65 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 50: OLOGIC Switching Characteristics
Symbol
Description
Setup/Hold
T_ODCK/T_OCKD
D1/D2 pins Setup/Hold with respect to CLK
T_OOCECK/T_OCKOCE OCE pin Setup/Hold with respect to CLK
T_OSRCK/T_OCKSR
SR pin Setup/Hold with respect to CLK
T_OTCK/T_OCKT
T1/T2 pins Setup/Hold with respect to CLK
T_OTCECK/T_OCKTCE
TCE pin Setup/Hold with respect to CLK
Combinatorial
T_DOQ
Sequential Delays
T_OCKQ
T_RQ
T_GSRQ
Set/Reset
T_RPW
D1 to OQ out or T1 to TQ out
CLK to OQ/TQ out
SR pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR inputs
-3
0.45/
–0.08
0.17/
–0.03
0.59/
–0.24
0.44/
–0.07
0.15/
–0.04
0.78
0.54
0.80
7.60
0.78
Speed Grade
Units
-2
-1 (XC) -1 (XQ) -1L
0.50/
0.54/
0.54/
0.69/
ns
–0.08 –0.08 –0.08 –0.11
0.20/
0.22/
0.27/
0.27/
ns
–0.03 –0.03 –0.05 –0.04
0.62/
0.54/
0.54/
0.79/
ns
–0.24 –0.08 –0.08 –0.35
0.51/
0.56/
0.60/
0.68/
ns
–0.07 –0.07 –0.10 –0.13
0.19/
0.21/
0.27/
0.29/
ns
–0.04 –0.04 –0.05 –0.05
0.87
1.01
1.01
1.15
ns
0.61
0.71
0.71
0.80
ns
0.90
1.05
1.05
1.19
ns
7.60
10.51 10.51 10.51
ns
0.95
1.20
1.20
1.30 ns, Min
DS152 (v3.5) May 17, 2013
www.xilinx.com
Product Specification
38