EN005 Datasheet, PDF (3/4 Pages) Xilinx, Inc – Virtex-4 XC4VFX12CES Errata

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Virtex-4 XC4VFX12CES Errata
Workaround
Compile code with the Xilinx provided Gnu compiler to achieve full frequency (350 MHz for -10 speed grade;
400 MHz -11 speed grade). For details, see answer record 21075.
When using all other compilers, the frequency is as stated in item 1.
2) When using the APU controller interface, the maximum operating frequency of the processor block is 275 MHz,
for -10 speed grade and 300 MHz for -11 speed grade.
For other processor block errata and operational guidelines, refer to answer record 20658.
Operational Guidelines
Design Software Requirements
The devices covered by these errata, unless otherwise specified, require the following Xilinx development software
installations.
• Speed specification v1.57 (or later) and Xilinx software ISE 7.1i Service Pack 4 (SP4) or later is required when
designing for the devices covered by this errata. Contact Xilinx technical support for SP4 help. Updates are
available on the following web page:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The Stepping should be set to "ES" in the constraint file (UCF file):
CONFIG STEPPING = "ES";
• A summary list of ISE software known issues pertaining to the Virtex-4 features is available at:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=19713
Notes and Recommendations
Virtex-II and Virtex-II Pro FPGA Designers
For Virtex-II and Virtex-II Pro designers, the CCLK specification in Virtex-4 devices was changed to LVCMOS 12mA
Fast slew rate. Xilinx recommends designing to this new standard.
Traceability
The XC4VFX12 is marked as shown in Figure 1.
Device Type
Package
Speed Grade
®
Virtex™-4
XC4VFX12 ^™
FF668 xxx XXXX
xxxxxxxxx
10C- ES
Circuit Design Revision
Axx: JTAG ID = 0
Dxx: JTAG ID = 2
Date Code
Lot Code
Engineering Sample
Operating Range
Figure 1: Example XC4VFX12CES Package Marking
EN005 (v1.2) February 21, 2006
www.xilinx.com
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Errata Notification