EN005 Datasheet, PDF (2/4 Pages) Xilinx, Inc – Virtex-4 XC4VFX12CES Errata

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Virtex-4 XC4VFX12CES Errata
available on the following web page:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The Stepping should be set to "0" in the constraint file (UCF file):
CONFIG STEPPING = "0";
• A summary list of ISE software known issues pertaining to the Virtex-4 features is available at:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=19713
Notes and Recommendations
Virtex-II and Virtex-II Pro FPGA Designers
For Virtex-II and Virtex-II Pro designers, the CCLK specification in Virtex-4 devices was changed to LVCMOS 12mA
Fast slew rate. Xilinx recommends designing to this new standard.
Hardware Errata Details (JTAG ID = 0)
This section provides a detailed description of each hardware issue known at the release time of this document for devices
where JTAG ID = 0.
FIFO16
The errata for JTAG ID = 0 is the same as the errata for JTAG ID = 2. See FIFO16, page 1.
DSP48
CarryIn Input Register
The CarryIn input register from fabric is not supported (that is, the attribute CARRYINREG = 1).
Workaround
Use the CLB register to replace the CarryIn input register, and set attribute CARRYINREG = 0.
Symmetric Rounding Logic
The DSP48 element supports five different modes of symmetric rounding. All four non-pipelined rounding modes
are fully supported. Only the pipelined Round (A x B) mode (that is, when CarryInSel[1:0] = 11) is not
supported.
Workaround
Perform the equivalent logic for carry in a CLB, and connect the carry to the CarryIn input of the DSP48 using
CarryInSel[1:0] = 00 (set attribute CARRYINREG = 0).
DCM
1. The DCM attribute CLKOUT_PHASE_SHIFT set to the value VARIABLE_CENTER is not supported.
2. If the only clock outputs used from a DCM are CLKFX and/or CLKFX180, and the input clock frequency (CLKIN) is
outside of the CLKIN_FREQ_DLL_(HF or LF)_(MS or MR)_MIN/MAX range, then use the macro in answer record
20529 to properly generate the LOCKED signal.
3. For source-synchronous applications, it is best to use the ChipSync™ features for the highest performance and
lowest skew. If the DCM must be used, follow the guidelines outlined in answer record 20529 to achieve a
CLKIN_CLKFB_PHASE specification of ±300 ps.
Processor Block
Frequency Performance
1) The Power PC™405 processor (PPC405) core maximum operating frequency is 300 MHz for -10 speed grade
and 350 MHz for -11 speed grade.
2
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EN005 (v1.2) February 21, 2006
Errata Notification