XCV405E-6BG560C Datasheet, PDF (22/116 Pages) Xilinx, Inc – 294 Kb of internal configurable distributed RAM

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
R
Vcc
TPOR
PROGRAM
INIT
TPL
CCLK OUTPUT or INPUT
TICCK
M0, M1, M2
(Required)
VALI
ds022_020_071201
Figure 20: Power-Up Timing Configuration Signals
The corresponding timing characteristics are listed in
Table 12.
Table 12: Power-up Timing Characteristics
Description
Symbol Value Units
Power-on Reset¹
Program Latency
CCLK (output) Delay
T_POR
T_PL
T_ICCK
2.0
100.0
0.5
4.0
ms, max
µs, max
µs, min
µs, max
Program Pulse Width T_PROGRAM 300 ns, min
Notes:
1. T_POR delay is the initialization time required after V_CCINT
reaches the recommended operating voltage.
Delaying Configuration
INIT can be held Low using an open-drain driver. An
open-drain is required since INIT is a bidirectional
open-drain pin that is held Low by the FPGA while the con-
figuration memory is being cleared. Extending the time that
the pin is Low causes the configuration sequencer to wait.
Thus, configuration is delayed by preventing entry into the
phase where data is loaded.
Readback
The configuration data stored in the Virtex-E configuration
memory can be readback for verification. Along with the
configuration data it is possible to readback the contents all
flip-flops/latches, LUT RAMs, and block RAMs. This capa-
Start-Up Sequence
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.
One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
bal Write Enable (GWE) signals are released. This permits
the internal storage elements to begin changing state in
response to the logic and the user clock.
The relative timing of these events can be changed. In addi-
tion, the GTS, GSR, and GWE events can be made depen-
dent on the DONE pins of multiple devices all going High,
forcing the devices to start synchronously. The sequence
can also be paused at any stage until lock has been
achieved on any or all DLLs.
bility is used for real-time debugging. For more detailed
information, see application note XAPP138 “Virtex FPGA
Series Configuration and Readback”.
Module 2 of 4
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DS025-2 (v2.1) July 17, 2002