XCV405E-6BG560C Datasheet, PDF (114/116 Pages) Xilinx, Inc – 294 Kb of internal configurable distributed RAM

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
R
Table 6: FG900 Differential Pin Pair Summary —
XCV812E
P
N
Other
Pair Bank Pin Pin AO
Functions
201 5 AC11 AG8 -
-
202 5 AK8 AF7 √
VREF
203 5 AG7 AK7 √
-
204 5 AJ7 AD10 -
-
205 5 AH6 AC10 -
-
206 5 AD9 AG6 √
VREF
207 5 AB10 AJ5 √
-
209 5 AC9 AJ4 √
-
210 5 AG5 AK4 √
-
212 6 AC6 AF3 √
-
214 6 AE4 AB9 √
-
215 6 AH1 AE3 -
-
217 6 AA10 AG1 -
-
218 6 AD4 AA9 √
VREF
219 6 AD2 AD5 √
-
220 6 AF2 AD3 -
-
221 6 AA7 AA8 -
-
222 6
Y9 AF1 √
VREF
223 6 AC4 AB6 √
-
224 6
W8 AE1 √
-
225 6 AB4 Y8
-
-
226 6
W9 AB3 -
VREF
228 6 V10 AB1 -
-
230 6 AA3 V11 -
-
232 6 AA6 W7 √
-
233 6
Y4
Y6
-
-
235 6
Y2
Y3
-
-
236 6
W5 Y5
√
VREF
237 6
W6 W4
√
-
238 6
W2 V6
-
-
239 6
V4
U9
-
-
240 6
T8 AB2 √
VREF
241 6
W1 U5
√
-
242 6
T9
Y1
√
-
243 6
U3 T7
-
-
244 6
V2
T5
-
VREF
246 6
U2 T4
-
-
Table 6: FG900 Differential Pin Pair Summary —
XCV812E
P
N
Other
Pair Bank Pin Pin AO
Functions
247 7 R10 T1
-
IRDY
249 7
R4 R8
-
-
250 7
R3 R7
-
-
251 7
P6 P10 -
VREF
252 7
P2
P5
-
-
253 7
P4
P7
√
-
254 7
R2 N4
√
-
255 7
P1 N7
√
VREF
256 7
N6 M6
-
-
257 7
N1 N5
-
-
258 7
M5 M4
√
-
259 7
M1 M2
√
VREF
260 7
L2
L4
-
-
262 7
M8 L1
-
-
263 7
M9
K2
√
-
265 7
K1
K5
√
-
266 7
K3
L6
√
VREF
267 7
K4
L7
-
-
268 7
J5
L8
-
-
269 7
H4
K6
-
VREF
270 7
K7 H1
-
-
271 7
J2
J7
√
-
272 7
G2 H5
√
-
273 7
G5
L9
√
VREF
274 7
K8
F3
-
-
275 7
E1 G3
-
-
276 7
E2 H6
√
-
277 7
K9
E4
√
VREF
278 7
F4
J8
-
-
280 7
C2 G6
-
-
281 7
F5
D2
-
-
Module 4 of 4
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DS025-4 (v1.6) July 17, 2002