XCV405E-6BG560C Datasheet, PDF (13/116 Pages) Xilinx, Inc – 294 Kb of internal configurable distributed RAM

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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Figure 11 is a diagram of the Virtex-E Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE
1149.1 Test Access Port controller, and the Instruction Register with decodes.
IOB IOB IOB IOB IOB
IOB.T
DATA IN
1
0
D
Q
0
sd
D
Q
1
LE
IOB
IOB
IOB
IOB
IOB
IOB
IOB
TDI
BYPASS
REGISTER
INSTRUCTION REGISTER
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M TDO
U
X
IOB.I
IOB.Q
IOB.T
1
D
Q
0
1
D
Q
0
1
D
Q
0
sd
D
Q
LE
1
0
sd
D
Q
LE
1
0
0
sd
D
Q
1
LE
IOB.I
1
D
Q
0
sd
D
Q
LE
DATAOUT
SHIFT/
CAPTURE
CLOCK DATA
REGISTER
UPDATE
Figure 11: Virtex-E Family Boundary Scan Logic
1
0
EXTEST
X9016
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
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