X68C75 Datasheet, PDF (8/26 Pages) Xicor Inc. – Port Expander and E2 Memory

X68C75 SLIC^® E²
Programmable Address Decoding
The X68C75 features an internal programmable ad-
dress decoder which allows the nonvolatile memory
array and the internal registers to be mapped in various
locations of the 64K-byte memory map. The register set
is mappable into a 1K-byte block, while the nonvolatile
memory array is mappable into an 8K-byte block. The
mapping is controlled by two nonvolatile configuration
registers, the SFR Map Register and the E² Memory
Map Register. Their bits are mapped as follows:
SFR Map Register (SFRM) Default = 81
7
6
1
0
A15-A10
5
A15
4
A14
3
A13
2
A12
1
0
A11 A10
2899 ILL F08
A15-A10 are upper address bits for the 1K-byte page
where the SFR memory is mapped.
BITS 7:6
Setting these two bits to any combination other than “10”
will interfere with device proper operation.
E² Memory Map Register (EEM) Default = 07
7
6
5
4
3
2
1
0
0
0 LAM 0 RST A15 A14 A13
2899 ILL F09
A15-A13
Modifying these three bits changes the location of the
program memory within the address map.The A15-A13
correspond to the upper three address bits of the 8K-
byte page where program memory will be mapped.
RST
The RST bit controls the polarity of the RESET input pin.
“0” = RESET is Active LOW
“1” = RESET is Active HIGH
LAM
Port B can be configured as either a general purpose
I/O port (normal I/O mode), or latched address mode
(LAM). The LAM option programs port B to output the
demultiplexed low order byte of the address latched into
the X68C75 by AS. The LAM bit selects between these
two modes.
“0” = Port B is an I/O Port
“1” = Port B outputs low address byte (A7-A0)
Setting the Mapping Registers
The mapping registers are written using a modified
version of the Software Data Protection sequence. All
timings must adhere to the normal Software Data
Protection sequence.
Figure 8. Setting the SFR Map Register
AA
b2 b1 b0 P 555
55
b2 b1 b0 P AAA
A0
b2 b1 b0 P 555
AA
b2 b1 b0 P 555
D0
b2 b1 b0 P AAA
Desired
Value
b2 b1 b0 P XXX
Delay of t_WC
Exit Routine
X = Don’t Care
B[2:0] = E2M [2:0]
P = Address bit (A12) of the
memory plane not being read.
2899 ILL F10.1
Figure 9. Setting Program Memory Map Register
AA
b2 b1 b0 P 555
55
b2 b1 b0 P AAA
A0
b2 b1 b0 P 555
AA
b2 b1 b0 P 555
E0
b2 b1 b0 P AAA
Desired
Value
b2 b1 b0 P XXX
Delay of t_WC
Exit Routine
X = Don’t Care
B[2:0] = E2M [2:0]
P = Address bit (A12) of the
memory plane not being read.
2899 ILL F11.1
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