X68C75 Datasheet, PDF (3/26 Pages) Xicor Inc. – Port Expander and E2 Memory

X68C75 SLIC^® E²
The X68C75 write control input, serves as an external
control over the completion of a previously initiated page
load cycle.
The X68C75 also features the industry standard 5V E²
memory characteristics such as byte or page mode write
and Toggle Bit Polling.
Read
A HIGH to LOW transition on AS latches the address;
the data will be output on the AD pins when E clock and
R/W are HIGH (t_ACC).
Write
A write is performed by latching the address on the
falling edge of AS. The R/W signal LOW while E clock is
HIGH initiates a write cycle. The valid data must be
present on AD₀-AD₇ prior to an E clock HIGH to LOW
transition. The data will be latched into the X68C75 on
the falling edge of E clock.
Page Write Operation
The X68C75 supports page mode write operations. This
allows the microcontroller to write from one to thirty-two
bytes of data to the X68C75. Each individual write within
a page write operation must conform to the byte write
timing requirements. The rising edge of E clock starts a
timer delaying the internal programming cycle 100µs,
therefore, each successive write operation must begin
within 100µs of the last byte written. The waveform
on page 19 illustrates the sequence and timing
requirements.
Toggle Bit Polling
Because the X68C75 typical write timing is less than the
specified 5ms, Toggle Bit Polling has been provided to
PIN DESCRIPTIONS
PIN NAME
I/O DESCRIPTION
A15–A8
AD7–AD0
AS
CE
E
IRQ
PA7–PA0
PB7–PB0
R/W
RESET
SEL
STRA, STRB
WC
I Non-multiplexed high-order Address line inputs for the upper byte of the address. The addresses are
latched when AS makes a HIGH to LOW transition.
I/O Multiplexed lower-order Address and DATA lines. The addresses are latched when AS makes a
HIGH to LOW transition.
I Address Strobe input is used to latch the addresses present on the address lines A15–A8 and AD7–
AD0 into the device. The addresses are latched when AS transitions from HIGH to LOW.
I The device select (CE) is an active HIGH input. This signal has to be asserted prior to AS HIGH to
LOW transition in order to generate a valid internal device select signal. Holding this pin LOW and
AS LOW will place the device in standby mode. The ports stay active at all times.
I The E clock is the bus frequency clock input, and is used as a data timing reference signal. When
the E clock is LOW, the addresses are latched by HIGH to LOW transition on the AS pin. The E
clock HIGH cycle is used for data transfers.
O The IRQ is an open-drain output. It can be configured to signal latching of new data into the ports,
and completion of an E² memory write cycle.
I/O The I/O lines of port A. The output driver can be configured as either CMOS or open-drain using the
AWO bit in CR. The I/O direction bit (DIRA) in CR is used to select the port A I/O mode.
I/O The I/O lines of port B. The output driver can be configured as either CMOS or open-drain using the
BWO bit in CR. The I/O direction bit (DIRB) in CR is used to select the port B I/O mode.
I The R/W signal indicates the direction of data transfers. During phase 2 (HIGH cycle) of the E clock,
the R/W is HIGH for a read, and LOW for a write cycle.
I RESET is used to initialize the internal static registers and has no effect on the E² memory opera-
tions. The default active level is LOW, but it can be reconfigured in EEM register.
I The SEL input should be LOW for the device to be selected. This input is normaly tied to VSS.
I/O The STRA controls port A and STRB controls port B. When ports are configured as inputs, a valid
transition on their strobe pins will latch into their Port Data Register the data present at the port input
pins. Writing to an output port Data Register generates a pulse of fixed duration on its corresponding
strobe pin. The output data presented at the output pins stay valid until the next data is written to the
output port data register.
I WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order to
disable writes to the E² memory. Taking the WC HIGH prior to tBLC (100µs; the time delay from the
last write cycle to the start of internal programming cycle) will inhibit the write operation.
2899 PGM T01.1
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