X5043 Datasheet, PDF (8/20 Pages) Xicor Inc. – CPU Supervisor with 4K SPI EEPROM

X5043/X5045
Figure 8. Read EEPROM Array Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
12 13 14 15 16 17 18 19 20 21 22
Instruction
SI
8
8 Bit Address
76 5
3 21 0
High Impedance
SO
9^th Bit of Address
Data Out
7 65 4 3 2 10
MSB
Write Memory Array
Prior to any attempt to write data into the memory
array, the “Write Enable” Latch (WEL) must be set by
issuing the WREN instruction (Figure 5). First pull CS
LOW, then clock the WREN instruction into the device
and pull CS HIGH. Then bring CS LOW again and
enter the WRITE instruction followed by the 8-bit
address and then the data to be written. Bit 3 of the
WRITE instruction contains address bit A₈, which
selects the upper or lower half of the array. If CS does
not go HIGH between WREN and WRITE, the WRITE
instruction is ignored.
The WRITE operation requires at least 16 clocks. CS
must go low and remain low for the duration of the
operation. The host may continue to write up to 16
bytes of data. The only restriction is that the 16 bytes
must reside within the same page. A page address
begins with address [x xxxx 0000] and ends with [x
xxxx 1111]. If the byte address reaches the last byte on
the page and the clock continues, the counter will roll
back to the first address of the page and overwrite any
data that has been previously written.
For the write operation (byte or page write) to be com-
pleted, CS must be brought HIGH after bit 0 of the last
complete data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 9).
While the write is in progress following a status register
or memory array write sequence, the Status Register
may be read to check the WIP bit. WIP is HIGH while
the nonvolatile write is in progress.
REV 1.1.2 5/29/01
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Characteristics subject to change without notice. 8 of 20