X5043 Datasheet, PDF (7/20 Pages) Xicor Inc. – CPU Supervisor with 4K SPI EEPROM

X5043/X5045
Table 2. Device Protect Matrix
WREN CMD
(WEL)
0
x
1
Device Pin
(WP)
x
0
1
Memory Block
Protected Area
Unprotected Area
Protected
Protected
Protected
Protected
Protected
Writable
Figure 6. Read Status Register Sequence
CS
Status Register
(BL0, BL1, WD0, WD1)
Protected
Protected
Writable
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
High Impedance
SO
Data Out
76543210
MSB
Figure 7. Write Status Register Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
Data Byte
7 6 5 43 2 1 0
High Impedance
SO
Read Memory Array
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
8-bit address. Bit 3 of the READ instruction selects the
upper or lower half of the device. After the READ
opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO line. The data stored in memory at the next
address can be read sequentially by continuing to pro-
vide clock pulses. The address is automatically incre-
mented to the next higher address after each byte of
data is shifted out. When the highest address is
reached, the address counter rolls over to address
$000 allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by taking CS
high. Refer to the Read EEPROM Array Sequence
(Figure 8).
REV 1.1.2 5/29/01
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Characteristics subject to change without notice. 7 of 20