X24641 Datasheet, PDF (6/13 Pages) Xicor Inc. – 400 KHz 2-Wire Serial E 2 PROM

X24641
WRITE OPERATIONS
Byte Write
For a Byte Write Operation, the device requires the
Slave Address Byte, the Word Address Byte 1, and
the Word Address Byte 0, which gives the master
access to any one of the bytes in the array. Upon
receipt of the Word Address Byte 0, the device
responds with an acknowledge, and waits for the first
eight bits of data. After receiving the 8 bits of the data
byte, the device again responds with an acknowl-
edge. The master then terminates the transfer by
generating a stop condition, at which time the device
begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress
the device inputs are disabled and the device will not
respond to any requests from the master. The SDA
pin is at high impedance. See figure 4.
Page Write Operation
The device executes a thirty-two byte Page Write
Operation. For a Page Write Operation, the device
requires the Slave Address Byte, Address Byte 1, and
Address Byte 0. Address Byte 0 must contain the first
byte of the page to be written. Upon receipt of Address
Byte 0, the device responds with an acknowledge, and
waits for the first eight bits of data. After receiving the 8
bits of the first data byte, the device again responds
with an acknowledge. The device will respond with an
acknowledge after the receipt of each of 31 more
bytes. Each time the byte address is internally incre-
mented by one, while page address remains constant.
When the counter reaches the end of the page, the
master terminates the data loading by issuing a stop
condition, which causes the device to begin the
nonvolatile write cycle. All inputs are disabled until
completion of the nonvolatile write cycle. The SDA pin
is at high impedance. Refer to figure 5 for the address,
acknowledge, and data transfer sequence.
Figure 4. Byte Write Sequence
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
S
T
A
R
SLAVE
ADDRESS
T
S1 0 1 0
0
WORD ADDRESS WORD ADDRESS
BYTE 1
BYTE 0
A
A
A
C
C
C
K
K
K
DATA
S
T
O
P
P
A
C
K
7026 FM 07
Figure 5. Page Write Sequence
S
SIGNAL_SS_IGNALS T
FROM TFHREOM THEA
MASTEMRASTER R
T
S
AD_RAT^SDLARVE_A^ES_DSS_DLARVEESS
T
ADB_WYDTROEERS_B1DS_YATDED1RESSADB_WYDTOREE_RS_{DB0SYATDED0RESS}
DATA
(1)
DATA
SDA BU_SS_{DA BUS} S 1 0 1_S 0_{1 0 1 0} 0
0
SIGNAL_SS_IGNALS
FROM TFHREOM THE
SLAVE SLAVE
AA
AA
AA
A
CC
CC
CC
C
KK
KK
KK
K
S^DATA
S
T(32)
T
O
O
P
P
P
P
A
A
C
C
K
K
7026 FM₇₀0₁7_{2 ILL F08.1}
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