X86C64 Datasheet, PDF (5/12 Pages) Xicor Inc. – E2 Micro-Peripheral

X86C64
Toggle Bit Polling
Because the X86C64 typical write timing is less than the
specified 5 ms, Toggle Bit Polling has been provided to
determine the early end of write. During the internal
programming cycle I/O₆ will toggle from one to zero and
zero to one on subsequent attempts to read the device.
Toggle Bit Polling DS Control
When the internal cycle is complete the toggling will
cease and the device will be accessible for additional
read or write operations. Due to the dual plane architec-
ture, reads for polling must occur in the plane that was
written; that is, the state of A₁₂ during write must match
the state of A₁₂ during polling.
OPERATION
CE
LAST BYTE
WRITTEN
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X68C64 READY FOR
NEXT OPERATION
AS
A/D0–A/D7
AIN DIN
AIN DOUT
AIN DOUT
AIN DOUT
AIN DOUT
AIN
A8–A12
A12=n
A12=n
A12=n
A12=n
A12=n
ADDR
DS
R/W
3819 FHD F08
5