X86C64 Datasheet, PDF (4/12 Pages) Xicor Inc. – E2 Micro-Peripheral

X86C64
MODE SELECTION
CE
DS
VSS
X
VIL
X
V_IH
V_IL
VIH
R/W
X
X
V_IH
VIL
Mode
Standby
Standby
Read
Write
I/O
High Z
High Z
D_OUT
DIN
Power
Standby (CMOS)
Standby (TTL)
Active
Active
3819 PGM T08
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X86C64
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X86C64. Each individual write within a page
write operation must conform to the byte write timing
requirements. The falling edge of DS starts a timer
delaying the internal programming cycle 100 µs. There-
fore, each successive write operation must begin within
100 µs of the last byte written. The following waveforms
illustrate the sequence and timing requirements.
Page Write Timing Sequence for DS Controlled Operation
OPERATION
CE
AS
A/D0–A/D7
A8–A12
DS
BYTE 0
AIN DIN
A12=n
BYTE 1
AIN DIN
A12=n
BYTE 2
LAST BYTE
READ (1)(2)
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=x
AFTER tWC READY FOR
NEXT WRITE OPERATION
AIN
ADDR
AIN
Next Address
R/W
tBLC
tWC
381398F1H9DFFH07D F07
Notes: (1) For each successive write within a page write cycle A₅–A₁₂ must be the same.
(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page
write operation. Two responses are possible.
a. Reading from the same plane being written (A₁₂ of Read = A₁₂ of Write) is effectively a Toggle Bit Polling operation.
b. Reading from the opposite plane being written (A₁₂ of Read ≠ A₁₂ of Write) true data will be returned, facilitating the use of a
single memory component as both program and data store.
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