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| X88257 Datasheet, PDF (3/15 Pages) Xicor Inc. – E2 Micro-Peripheral | |||
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X88257
TYPICAL APPLICATION
U?
31 EA/VP
19 X1
18 X2
9 RESET
12 INT0
13 INT1
14 T0
15 T1
1 P1.0
2 P1.1
3 P1.2
4 P1.3
5 P1.4
6 P1.5
7 P1.6
8 P1.7
8051
P0.0 39
P0.1 38
P0.2 37
P0.3 36
P0.4 35
P0.5 34
P0.6 33
P0.7 32
P2.0 21
P2.1 22
P2.2 23
P2.3 24
P2.4 25
P2.5 26
P2.6 27
P2.7 28
RD 17
WR 16
PSEN 29
ALE/P 30
TXD 11
RXD 10
11 A/D0
12 A/D1
12 A/D2
15 A/D3
16 A/D4
17 A/D5
18 A/D6
19 A/D7
25 A8
24 A9
21 A10
23 A11
2 A12
26 A13
1 A14
20 CE
22 RD
27 WR
4 PSEN
3 ALE
CE 5
X88257
6509 ILL F03.3
PRINCIPLES OF OPERATION
The X88257 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The X88257
provides 32K-bytes of 5V E2PROM which can be used
either for program storage, data storage or a combina-
tion of both, in systems based upon Harvard (80XX)
architectures. The X88257 incorporates the interface
circuitry normally needed to decode the control signals
and demultiplex the address/data bus to provide a
âseamlessâ interface.
The interface inputs on the X88257 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip micro-
controller. In the Harvard type system, the reading of
data from the chip is controlled either by the PSEN or the
RD signal, which essentially maps the X88257 into both
the Program and the Data Memory address map.
The X88257 also features the industry standard 5V
E2PROM characteristics such as byte or page mode
write and Toggle Bit Polling.
DEVICE OPERATION
ModesâMixed Program/Data Memory
By properly assigning the address spaces, a single
X88257 can be used as both the program and data
memory. This would be accomplished by connecting all
the 8051 control outputs to the corresponding inputs of
the X88257.
Program Memory Mode
This mode of operation is read-only. The PSEN and ALE
inputs of the X88257 are tied directly to the PSEN and
ALE outputs of the microcontroller. The RD and WR
inputs are tied HIGH.
When ALE is HIGH, the A/D0âA/D7 and A8âA14 ad-
dresses flow into the device. The addresses, both low-
and high-order, are latched when ALE transitions LOW
(VIL). PSEN will then go LOW and after tPLDV; Valid data
is presented on the A/D0âA/D7 pins. CE must be LOW
during the entire operation.
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