X88257 Datasheet, PDF (2/15 Pages) Xicor Inc. – E2 Micro-Peripheral

X88257
PIN DESCRIPTIONS
Address/Data (A/D₀–A/D₇)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while ALE is HIGH. After
ALE transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on RD, WR, PSEN,
and CE.
Addresses (A₈–A₁₄)
High order addresses flow into the device when ALE =
V_IH and are latched when ALE goes LOW.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, ALE is LOW, and
CE is LOW, the X88257 is placed in the low power
standby mode. If CE is used to select the device, the CE
must be tied LOW.
Chip Enable (CE)
Chip enable is active HIGH. When CE is used to select
the device, the CE must be tied HIGH.
Program Store Enable (PSEN)
When the X88257 is to be used in a 8051-based system,
PSEN is tied directly to the microcontroller’s PSEN
output.
Read (RD)
When the X88257 is to be used in a 8051-based system,
RD is tied directly to the microcontroller’s RD output.
Write (WR)
When the X88257 is to be used in a 8051-based system,
WR is tied directly to the microcontroller’s WR output.
Address Latch Enable (ALE)
Addresses flow through the latches to address decoders
when ALE is HIGH and are latched when ALE transitions
from a HIGH to LOW.
PIN CONFIGURATION
PDIP
SOIC
A14
A12
ALE
PSEN
CE
NC
NC
NC
NC
NC
A/D0
A/D1
A/D2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7 ^X88257 22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
PLCC
VCC
WR
A13
A8
A9
A11
RD
A10
CE
A/D7
A/D6
A/D5
A/D4
A/D3
6509 FHD F01.3
PSEN
CE
NC
NC
NC
NC
NC
NC
A/D0
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
X88257
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
A8
A9
A11
NC
RD
A10
CE
A/D7
A/D6
PIN NAMES
Symbol
ALE
A/D0–A/D7
A₈–A₁₄
RD
WR
PSEN
CE, CE
VSS
V_CC
NC
6509 FHD F01A.5
Description
Address Latch Enable
Address Inputs/Data I/O
Address Inputs
Read Input
Write Input
Program Store Enable Input
Chip Enable
Ground
Supply Voltage
No Connect
6509 PGM T01.1
2