X46402 Datasheet, PDF (3/23 Pages) Xicor Inc. – Dual Voltage CPU Supervisor with 64K Password Protected EEPROM

X46402
Preliminary Information
Volt
Reg
OTP Mode
Enabled
Pin1
Vss
WP
Vcc
V2MON
SDA
SCL
RESET ^V2FAIL
Recommended Connection
µC
Vcc
SCL
SDA
INTR
RESET
ARCHITECTURE
Data Memory
This 64kbit memory array can be partitioned into pass-
word protected or non-password protected areas. When
password protected, the contents are readable after
sending a “Memory Read” password. The contents of a
password protected portion of the memory array are
writeable with a “Memory Write” Password. This array is
re-writable up to the limit of the EEPROM endurance.
OTP
The second section of memory consists of two 64-byte
arrays, each writable only once. These arrays are always
password protected. Reading from either of these arrays
requires the use of an “OTP Read” password. Both
arrays can be read with a single operation. Writing either
array requires an “OTP Write” Password. Writing more
than 64 bytes to each array results in the data “wrapping”
around and over-writing previous values.
Array
OTP Array 1
OTP Array 2
Address
0000h - 003Fh
0040h - 007Fh
Control Register
A password protected read or write array command at
address FFFFh reads or writes the Control Register.
Since the control register contains information relating to
the password protection, it is necessary to use the Array
passwords to access the control register.
The Control Register contains bits that control the watch-
dog timer and the hardware write protect features and is
formatted as follows:
7
654
321
0
WPEN FLB WD2 WD1 WD0 BL2 BL1 BL0
Write Protect Enable bit (WPEN)
The WP pin, in conjuction with a WPEN bit programmed
HIGH, provides Hardware Write Protection. This prevents
changes to the control register contents even with a valid
password. When either the WP pin or WPEN bit is LOW,
a 64 bit Array write array password is required to change
the contents of the control register. When both the WP
pin and the WPEN bit are HIGH, the Control Register
cannot be written.
Flag Bit
The flag bit is a volatile bit. It can be used to determine if
a reset condition was due to a power failure or watchdog
reset condition. If power fails (i.e. the internal low voltage
detect signal goes active), the bit is set to ’0’. This bit is
also set or reset by a Control Register write operation. A
watchdog reset does not change the state of the flag bit.
Watchdog Timer Control
The Watchdog time-out period is controlled by the bits
WD2, WD1, and WD0. See the following Table.
Table 1. Watchdog Time Control Bits
Control Register Bits
WD2 WD1 WD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Watchdog Time-out
(Typical)
1 Second
450 Milliseconds
150 Milliseconds
Disabled
1 minute
20 seconds
10 seconds
5 seconds
3