X28C64 Datasheet, PDF (13/25 Pages) Xicor Inc. – 5 Volt, Byte Alterable E2PROM

X28C64
WRITE CYCLE LIMITS
Symbol
tWC(5)
tAS
t_AH
tCS
tCH
t_CW
tOES
tOEH
t_WP
tWPH
tWPH2(6)
t_DV
tDS
tDH
t_DW
tBLC(7)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
SDP WE Recovery
Data Valid
Data Setup
Data Hold
Delay to Next Write
Byte Load Cycle
WE Controlled Write Cycle
ADDRESS
CE
tAS
tAH
tCS
Min.⁽⁷⁾
0
100
0
0
100
10
10
100
200
1
50
10
10
1
Typ.⁽¹⁾
5
tWC
tCH
Max.
10
1
100
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
µs
3853 PGM T11.1
OE
WE
DATA IN
DATA OUT
tOES
tDV
tOEH
tWP
DATA VALID
tDS
tDH
HIGH Z
3853 FHD F06
Notes: (5) t_WC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
(6) t_WPH is the normal page write operation WE recovery time. t_WPH2 is the WE recovery time needed only after the end of issuing
the three-byte SDP command sequence and before writing the first byte of data to the array. Refer to Figure 6 which illustrates
the t_WPH2 requirement.
(7) For faster t_WC and t_BLC times, refer to X28HC64.
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