X24645 Datasheet, PDF (13/18 Pages) Xicor Inc. – Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection

X24645
Bus Timing
SCL
SDA IN
tSU:STA
tF
tHIGH
tLOW
tHD:STA tHD:DAT
tSU:DAT
tR
tSU:STO
tAA
tDH
tBUF
SDA OUT
2783 ILL F17
Write Cycle Limits
Symbol
T_WR(6)
Parameter
Write Cycle Time
Min.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle, the
Bus Timing
Typ.⁽⁵⁾
Max.
Units
5
10
ms
2783 FRM T11
X24645 bus interface circuits are disabled, SDA is
allowed to remain HIGH, and the device does not
respond to its slave address.
SCL
SDA
8th BIT
ACK
WORD n
tWR
STOP
CONDITION
START
CONDITION
2783 ILL F18
Notes: (5) Typical values are for T_A = 25°C and nominal supply voltage (5V).
(6) t_WR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
120
100
RMIN
=
VCC _MAX
IOL _MIN
=1.8KΩ
80
RMAX
=
tR
CBUS
60
MAX.
RESISTANCE
40
20 _MIN.
RESISTANCE
0
0 20 40 60
80 100 120
BUS CAPACITANCE (pF)
2783 ILL F19
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
13