WM8961 Datasheet, PDF (93/116 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8961
Pre-Production
REGISTER BIT
ADDRESS
LABEL
R30 (1Eh)
8:7
CLK_TO_DIV[1:0]
Clocking 3
6:1 CLK_256K_DIV[5:0]
0
MANUAL_MODE
Register 1Eh Clocking 3
DEFAULT
DESCRIPTION
00
10_1111
1
Timeout/slow clock divider setting
00 : 125Hz
01 : 250Hz
10 : 500Hz
11 : 1kHz
256kHz clock divider setting
000000 : SYSCLK/1
000001 : SYSCLK/2
…
101111 : SYSCLK/48 (default)
…
111110 : SYSCLK/63
111111 : SYSCLK/64
Manual clock configuration Enable
0 = When low, use SAMPLE_RATE & CLK_SYS_RATE to allow
automatic configuration of system clock dividers. Excludes master
mode audio interface clocks.
1 = manual configuration of system clock dividers.
REGISTER
ADDRESS
R32 (20h)
ADCL signal
path
BIT
LABEL
5:4 LMICBOOST[1:0]
Register 20h ADCL signal path
DEFAULT
DESCRIPTION
00
Left microphone boost control
00 : 0dB
01 : 13dB
10 : 20dB
11 : 29dB
REGISTER
ADDRESS
R33 (21h)
ADCR signal
path
BIT
LABEL
5:4 RMICBOOST[1:0]
Register 21h ADCR signal path
DEFAULT
DESCRIPTION
00
Right microphone boost control
00 : 0dB
01 : 13dB
10 : 20dB
11 : 29dB
REGISTER BIT
LABEL
ADDRESS
R40 (28h)
LOUT2
volume
8
SPKVU
7
SPKLZC
6:0 SPKLVOL[6:0]
Register 28h LOUT2 volume
w
DEFAULT
DESCRIPTION
0
0
000_0000
Speaker PGA volume update
Left Speaker PGA zero cross enable
Left Speaker output PGA gain, 1dB steps
0000000 to 0101111 : Mute
0110000 : -73dB
…
1111001 : 0dB
…
1111111 : +6dB
PP, August 2009, Rev 3.1
93