WM8961 Datasheet, PDF (82/116 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8961
Pre-Production
REG
NAME
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0 DEFAULT
path
R40 (28h) LOUT2 volume 0
0
0
0
0
0
0 SPKVU SPKLZC
SPKLVOL[6:0]
0000h
R41 (29h) ROUT2 volume 0
0
0
0
0
0
0 SPKVU SPKRZC
SPKRVOL[6:0]
0000h
R47 (2Fh) Pwr Mgmt (3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0 TEMP_SHTUEMP_WA 0000h
T RN
R48 (30h) Additional
Control (4)
0
0
0
0
0
0
0
0
0
0
0
0
0
0 TSENSENMBSEL 0023h
R49 (31h) Class D Control 0
0
0
0
0
0
0
0 SPKR_ENSAPKL_ENA 0
0
0
0
0
0 0000h
1
R51 (33h) Class D Control 0
0
0
0
0
0
0
0
0
0
0
0
0 CLASSD_ACGAIN[2:0] 0003h
2
R56 (38h) Clocking 4
0
0
0
0
0
0
0
CLK_DCS_DIV[3:0]
CLK_SYS_RATE[3:0]
0 0106h
R57 (39h) DSP Sidetone 0 0
0
0
0
0
0
0
0
ADCR_DAC_SVOL[3:0] ADC_TO_DACR[1:0 0
0 0000h
R58 (3Ah) DSP Sidetone 1 0
0
0
0
0
0
0
0
ADCL_DAC_SVOL[3:0] ADC_TO_DACL[1:0] 0
0 0000h
R60 (3Ch)DC Servo 0
0
0
0
0
0
0
0
0 DCS_ENAD_CS_TRIG 0 DCS_TRDIGCS_ENAD_CS_TRIG 0 DCS_TRIG 0000h
CHAN_IN_LSTARTUP _SERIESC_HI AN_IN_RSTARTUP _SERIES_I
_INL
NL (K)
_INR
NR (K)
R61 (3Dh)DC Servo 1
0
0
0
0
0
0
0
0 DCS_ENAD_CS_TRIG 0 DCS_TRDIGCS_ENAD_CS_TRIG 0 DCS_TRIG 0000h
CHAN_HP_SLTARTUP _SERIESC_HAN_HP_RSTARTUP _SERIES_H
_HPL
PL
_HPR
PR
R63 (3Fh) DC Servo 3
0
0
0
0
0
0
0
0
0
0 DCS_FILT_BW_SER 0
0
0
0 015Eh
IES[1:0]
R65 (41h) DC Servo 5
0
0
0
0
0
0
0
0
0
DCS_SERIES_NO_HP[6:0]
0010h
R68 (44h) Analogue PGA 0
0
0
0
0
0
0
0
0
0
0
0
0 HP_PGAS_BIAS[2:0] 0003h
Bias
R69 (45h) Analogue HP 0 0
0
0
0
0
0
0
0 HPL_RMVH_PL_ENAH_PL_ENAH_PL_ENHAPR_RMHVP_R_ENAH_PR_ENAH_PR_ENA 0000h
SHORT OUTP DLY
SHORT OUTP DLY
R71 (47h) Analogue HP 2 0
0
0
0
0
0
0
HPL_VOL[2:0]
HPR_VOL[2:0]
HP_BIAS_BOOST[2:0] 01FBh
R72 (48h) Charge Pump 1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 CP_ENA 0000h
R82 (52h) Charge Pump B 0
0
0
0
0
0
0
0
0
0
0
0
0
0 CP_DYN_PWR[1:0] 0000h
R87 (57h) Write Sequencer 0
0
0
0
0
0
0
0
0
0 WSEQ_EN
WSEQ_WRITE_INDEX[4:0]
1
A
0000h
R88 (58h) Write Sequencer 0
0
0
0
0
0
0 WSEQ_EO
2
S
WSEQ_ADDR[7:0]
0000h
R89 (59h) Write Sequencer 0
0
0
0
0
0
0
0
3
WSEQ_DATA[7:0]
0000h
R90 (5Ah) Write Sequencer 0
0
0
0
0
0
0 WSEQ_AWBSEQ_STA 0
4
ORT RT
WSEQ_START_INDEX[5:0]
0000h
R91 (5Bh) Write Sequencer 0
0
0
0
0
0
0
0
0 WSEQ_DATA_WIDTH[2:0] WSEQ_DATA_START[3:0] 0000h
5
R92 (5Ch)Write Sequencer 0
0
0
0
0
0
0
0
0
0
0
0
6
WSEQ_DELAY[3:0]
0000h
R93 (5Dh)Write Sequencer 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 WSEQ_BU 0000h
7
SY
R252 (FCh General test 1 0
0
0
0
0
0
0
0
0
0
0
0
0
0 ARA_ENAUTO_INC 0001h
w
PP, August 2009, Rev 3.1
82