WM8961 Datasheet, PDF (68/116 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8961
WM8961
WSEQ
REG
_LOCATION _INDEX
EOS
30
8’h45
1’b0
31
8’h45
1’b0
32
8’h02
1’b0
33
8’h03
1’b0
34
8’h03
1’b0
35
8’h28
1’b0
36
8’h29
1’b0
37
8’h29
1’b0
38
8’h3C
1’b0
39
8’h3D
1’b0
40
8’h1A
1’b0
41
8’h31
1’b0
42
8’h45
1’b0
43
8’h48
1’b0
44
8’h19
1’b0
45
8’h1C
1’b0
46
8’h19
1’b0
47
8’h08
1’b0
48
8’hFE
1’b1
Pre-Production
WIDTH START DATA
3’h4
4’h3 8’h0E
3’h4
4’h2 8’h0C
3’h6
4’h0 8’h00
3’h6
4’h0 8’h00
3’h0
4’h8 8’h01
3’h6
4’h0 8’h00
3’h6
4’h0 8’h00
3’h0
4’h8 8’h01
3’h4
4’h3 8’h00
3’h4
4’h3 8’h00
3’h5
4’h3 8’h00
3’h1
4’h6 8’h00
3’h5
4’h0 8’h00
3’h0
4’h0 8’h00
3’h5
4’h1 8’h00
3’h1
4’h3 8’h00
3’h1
4’h7 8’h00
3’h0
4’h4 8’h00
3’h0
4’h0 8’h00
DELAY
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
COMMENT
Clear RMV_SHRT on
outputs
Clear
HPL_ENA_OUTP &
HPR_ENA_OUTP
CUMULATIVE STARTUP
DELAY
TIME
0.0005
0.0180
0.0005
0.0185
LOUTVOL to mute
0.0005
0.0190
ROUTVOL to mute
0.0005
0.0195
OUT1VU
0.0005
0.0200
SPKLVOL to mute
0.0005
0.0205
SPKRVOL to mute
0.0005
0.0210
SPKVU
Disable Servo on
inputs
Disable Servo on
outputs
SPKL_PGA = 0,
SPKR_PGA = 0,
LOUT1_PGA = 0,
ROUT1_PGA = 0,
DACL = 0, DACR = 0
0.0005
0.0005
0.0005
0.0215
0.0220
0.0225
0.0005
0.0230
Disable Class D
Disable HPL_ENA,
HPR_ENA,
HPL_ENA_DLY,
HPR_ENA_DLY
0.0005
0.0235
0.0005
0.0240
Disable Charge Pump
VREF = 0 ; ADCL = 0 ;
ADCR = 0 ; MICB = 0 ;
AINL = 0 ; AINR = 0
BUFDCOPEN = 0,
BUFIOEN = 0 ;
Disable current bias
circuits
VMIDSEL = 00,
disable VMID
0.0005
0.0005
0.0005
0.0005
0.0245
0.0250
0.0255
0.0260
CLK_DSP_ENA = 0
Dummy Write for
expansion
0.0005
0.0005
0.0265
0.0270
Table 50 Write Sequencer Default Values (RAM =Locations 0-31, ROM = Locations 32-48)
w
PP, August 2009, Rev 3.1
68