WM8903 Datasheet, PDF (92/178 Pages) Wolfson Microelectronics plc – Ultra Low Power CODEC for Portable Audio Applications

WM8903
Production Data
When BCLK is not selected (GP5_FN ≠ 1), the WM8903 uses the MCLK input as the Bit Clock,
provided that BCLK_DIR is set to 0 to configure BCLK as an input, ie. BCLK slave mode. This
configuration can offer power consumption benefits in addition to flexibility of GPIO functionality,
When the BCLK pin is an output (BCLK_DIR=1), BCLK is derived from the internal CLK_SYS signal
(see “Clocking and Sample Rates”). In this case, the BCLK frequency is controlled in relation to
CLK_SYS by the BCLK_DIV register field. When BCLK is an input, BCLK_DIV has no effect.
When the LRC pin is an output (LRCLK_DIR=1), LRC is derived from BCLK (irrespective of whether
BCLK is an input or output). In this case, the LRC frequency is controlled in relation to BCLK by the
LRCLK_RATE register field. When LRC is an input, LRCLK_RATE has no effect.
BCLK_DIV and LRCLK_RATE are defined in Table 57. The clocking scheme is illustrated in the
“Clocking and Sample Rates” section - see Figure 55.
REGISTER
BIT
ADDRESS
LABEL
R25 (19h)
9
LRCLK_DIR
Audio Interface
1
6
BCLK_DIR
DEFAULT
0
0
R26 (1Ah)
4:0
Audio Interface
2
BCLK_DIV [4:0]
0_1000
R27 (1Bh)
10:0
Audio Interface
3
LRCLK_RATE
[10:0]
000_0010
_0010
Table 57 Digital Audio Interface Clock Control
DESCRIPTION
Audio Interface LRC Direction
0 = LRC is input
1 = LRC is output
Audio Interface BCLK Direction
0 = BCLK is input
1 = BCLK is output
BCLK Frequency (Master Mode)
00000 = CLK_SYS
00001 = Reserved
00010 = CLK_SYS / 2
00011 = CLK_SYS / 3
00100 = CLK_SYS / 4
00101 = CLK_SYS / 5
00110 = Reserved
00111 = CLK_SYS / 6
01000 = CLK_SYS / 8 (default)
01001 = CLK_SYS / 10
01010 = Reserved
01011 = CLK_SYS / 12
01100 = CLK_SYS / 16
01101 = CLK_SYS / 20
01110 = CLK_SYS / 22
01111 = CLK_SYS / 24
10000 = Reserved
10001 = CLK_SYS / 30
10010 = CLK_SYS / 32
10011 = CLK_SYS / 44
10100 = CLK_SYS / 48
LRC Rate (Master Mode)
LRC clock output = BCLK /
LRCLK_RATE
Integer (LSB = 1)
Valid range: 8 to 2047
50:50 LRCLK duty cycle is only
guaranteed with even values (8, 10,
… 2046).
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PD, Rev 4.5, June 2012
92