WM8580 Datasheet, PDF (81/92 Pages) Wolfson Microelectronics plc – Multichannel CODEC with S/PDIF Transceiver

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REGISTER BIT
ADDRESS
LABEL
7:6 CHNUM2[1:0]
R34
3:0
SPDTXCHAN 4
22h
5:4
FREQ[3:0]
CLKACU[1:0]
R35
0
SPDTXCHAN 5
23h
3:1
MAXWL
TXWL[2:0]
7:4
R36
0
SPDMODE
24h
ORGSAMP
[3:0]
SPDIFIN1MODE
2:1 RXINSEL[1:0]
R37
8:0
INTMASK
25h
MASK[8:0]
R38
3:0 GPO1OP[3:0]
w
DEFAULT
00
0001
11
1
101
0000
1
00
000000000
0000
DESCRIPTION
WM8580
11
0000 = Do not use channel number
Channel Number for Subframe 2
CHNUM2
Channel Status Bits[23:20]
00
0000 = Do not use channel number
01
0001 = Send to Left Channel
10
0010 = Send to Right Channel
11
0000 = Do not use channel number
Sampling Frequency. See S/PDIF specification for details.
0001 = Sampling Frequency not indicated.
Clock Accuracy of Generated clock.
00 = Level II
01 = Level I
10 = Level III
11 = Interface frame rate not matched to sampling frequency.
Maximum Audio sample word length
0 = 20 bits
1 = 24 bits
Audio Sample Word Length.
000 = Word Length Not Indicated
TXWL[2:0]
MAXWL==1
MAXWL==
0
001
20 bits
16 bits
010
22 bits
18 bits
100
23 bits
19 bits
101
24 bits
20 bits
110
21 bits
17 bits
All other combinations reserved
Original Sampling Frequency. See S/PDIF specification for details.
0000 = original sampling frequency not indicated
Selects the input circuit type for the SPDIFIN1 input
0 = CMOS-compatible input
1 = Comparator input. Compatible with 500mVpp AC coupled
consumer S/PDIF input signals as defined in IEC-60958-3.
S/PDIF Receiver input mux select. Note that the general purpose
inputs must be configured using GPOxOP to be either CMOS or
comparator inputs if selected by RXINSEL.
00 = SPDIFIN1
01 = SPDIFIN2 (MFP3)
10 = SPDIFIN3 (MFP4)
11 = SPDIFIN4 (MFP5)
When a flag is masked, it does not update the Error Register or
contribute to the interrupt pulse.
0 = unmask, 1 = mask.
MASK[0] = mask control for UPD_UNLOCK
MASK[1] = mask control for INT_INVALID
MASK[2] = mask control for INT_CSUD
MASK[3] = mask control for INT_TRANS_ERR
MASK[4] = mask control for UPD_AUDIO_N
MASK[5] = mask control for UPD_PCM_N
MASK[6] = mask control for UPD_CPY_N
MASK[7] = mask control for UPD_DEEMPH
MASK[8] = mask control for UPD_REC_FREQ
0000 = INTB
PP Rev 1.0 March 2006
81