WM8580 Datasheet, PDF (41/92 Pages) Wolfson Microelectronics plc – Multichannel CODEC with S/PDIF Transceiver

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WM8580
PRIMARY AUDIO INTERFACE RECEIVER (PAIF RX)
The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied
externally (slave mode) or they can be generated internally by the WM8580 (master mode). The
master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this
module is described on page 21. The clock supplied to this module is selected by the
PAIFRXMS_CLKSEL register bits and can be MCLK, PLLACLK, or PLLBCLK.
Figure 28 PAIF Receiver Clock Selection
REGISTER BIT
ADDRESS
R9
7:6
PAIF 1
09h
LABEL
PAIFRXMS_
CLKSEL
DEFAULT
00
Table 36 PAIF Receiver Master Mode Clock Control
DESCRIPTION
PAIF Receiver Master Mode clock
source
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
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PP Rev 1.0 March 2006
41