WM8580_07_12 Datasheet, PDF (77/97 Pages) Wolfson Microelectronics plc – Multichannel CODEC with S/PDIF Transceiver

Production Data
REGISTER BIT
ADDRESS
R4
8:0
PLLB 1
04h
R5
8:0
PLLB 2
05h
R6
3:0
PLLB 3
7:4
06h
LABEL
PLLB_K[8:0]
PLLB_K[17:9]
PLLB_K[21:18]
PLLB_N[3:0]
R7
PLLB 4
07h
0 PRESCALE_B
1 POSTSCALE_B
4:3 FREQMODE_B
[1:0]
6:5 MCLKOUTSRC
8:7 CLKOUTSRC
R8
CLKSEL
08h
1:0 DAC_CLKSEL
3:2 ADC_CLKSEL
DEFAULT
100100001
101111110
1101
0111
0
0
10
00
11
00
00
DESCRIPTION
WM8580
Fractional (K) part of PLLB frequency ratio (R).
Value K is one 22-digit binary number spread over registers R4,
R5 and R6 as shown.
Note: PLLB_K must be set to specific values when the S/PDIF
receiver is used. Refer to S/PDIF Receive Mode Clocking
section for details.
Integer (N) part of PLLB frequency ratio (R).
Use values in the range 5 ≤ PLLB_N ≤ 13 as close as possible to
8
Note: PLLB_N must be set to specific values when the S/PDIF
receiver is used. Refer to S/PDIF Receive Mode Clocking
section for details.
PLL Pre-scale Divider Select
0 = Divide by 1 (PLL input clock = oscillator clock)
1 = Divide by 2 (PLL input clock = oscillator clock ÷ 2)
Note: PRESCALE_A must be set to the same value as
PRESCALE_B in PLL S/PDIF receiver mode.
PLL Post-scale Divider Select
PLL S/PDIF Receiver Mode
POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK,
POSTSCALE_B is not used. Refer to Table 45.
PLL User Mode
Used in conjunction with the FREQMODE_x bits. Refer to Table
44.
PLL Output Divider Select
PLL S/PDIF Receiver Mode
FREQMODE_A is automatically controlled. FREQMODE_B is not
used.
PLL User Mode
Used in conjunction with the POSTSCALE_x bits. Refer to Table
44.
MCLK pin output source
00 = Input – Source MCLK pin
01 = Output – Source PLLACLK
10 = Output – Source PLLBCLK
11 = Output – Source OSCCLK
CLKOUT pin source
00 = No Output (tristate)
01 = Output – Source PLLACLK
10 = Output – Source PLLBCLK
11 = Output – Source OSCCLK
DAC clock source
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
ADC clock source
00 = ADCMLCK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
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PD Rev 4.3 August 2007
77