WM8580_07_12 Datasheet, PDF (43/97 Pages) Wolfson Microelectronics plc – Multichannel CODEC with S/PDIF Transceiver

Production Data
WM8580
REGISTER
ADDRESS
R8
CLKSEL
08h
BIT
LABEL
1:0 DAC_CLKSEL
R15
DAC
Control 1
0Fh
8 RX2DAC_MODE
Table 33 DAC Clock Control
DEFAULT
00
0
DESCRIPTION
DAC clock source
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
DAC oversampling rate and power down
control (only valid when DAC_SRC = 00,
DAC1 data sourced from S/PDIF receiver)
0 = SFRM_CLK determines
oversampling rate, DACs 2/3 powered
down
1 = PAIFRX_LRCLK determines
oversampling rate, DACs 2/3 source
PAIF Receiver
ADC INTERFACE
The ADC_CLKSEL register selects the ADC clock source from ADCMCLK, PLLACLK, PLLBCLK, or
MCLK. However, if the S/PDIF receiver is active, PLLACLK and PLLBCLK are invalid for ADC
operation, so the choice is limited to ADCMCLK (default) or MCLK.
The rate that the ADC operates at is determined by the ADC Rate module. It calculates the rate
based on the digital routing setup. If the ADC is sourced by the PAIF Transmitter, PAIFTX_LRCLK is
used in the rate calculation. If the ADC is sourced by the SAIF Transmitter (and PAIF Transmitter
has another source), SAIF_LRCLK is used in the rate calculation. If the S/PDIF Transmitter (only) is
sourcing the ADC, then the rate is set by the ADC_RATE register bits.
The ADC clock source can be independent from the DACs and PLLs, however for optimum
performance, it is recommended that where possible, clock sources on the WM8580 are
synchronous. Performance may be degraded if this condition is not met.
Figure 27 ADC Clock Selection
w
PD Rev 4.3 August 2007
43