WM8311 Datasheet, PDF (54/302 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8311
Pre-Production
In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field.
This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if
desired, the value of this field may be calculated by multiplying K by 2^16 and treating FLL_K as an
integer value, as illustrated in the following example:
If N.K = 8.192, then K = 0.192.
Multiplying K by 2^16 gives 0.192 x 65536 = 12582.912 (decimal) = 3126 (hex).
For best FLL performance, the FLL fractional mode is recommended. Therefore, if the calculations
yield an integer value of N.K, then it is recommended to adjust FLL_OUTDIV in order that N.K is a
non-integer value. Care must always be taken to ensure that the FLL operating frequency, FVCO, is
within its recommended limits of 90-100 MHz.
The register fields that control the FLL are described in Table 20.
ADDRESS
R16530 (4092h)
FLL Control 1
R16531 (4093h)
FLL Control 2
BIT
LABEL
2
FLL_FRAC
0
FLL_ENA
13:8 FLL_OUTDIV
[5:0]
6:4 FLL_CTRL_R
ATE [2:0]
DEFAULT
0
0
000000
000
DESCRIPTION
Fractional enable
0 = Integer Mode
1 = Fractional Mode
Integer mode offers reduced power
consumption. Fractional mode offers
best FLL performance, provided also
that N.K is a non-integer value.
FLL Enable
0 = Disabled
1 = Enabled
Note - this bit is reset to 0 when the
OFF power state is entered.
F_OUT clock divider
000000 = Reserved
000001 = Reserved
000010 = Reserved
000011 = 4
000100 = 5
000101 = 6
…
111110 = 63
111111 = 64
(F_OUT = F_VCO / FLL_OUTDIV)
Frequency of the FLL control block
000 = F_VCO / 1 (Recommended
value)
001 = F_VCO / 2
010 = F_VCO / 3
011 = F_VCO / 4
100 = F_VCO / 5
101 = F_VCO / 6
110 = F_VCO / 7
111 = F_VCO / 8
Recommended that this register is
not changed from default.
w
PP, May 2012, Rev 3.1
54