WM8311 Datasheet, PDF (166/302 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8311
Pre-Production
completion of the startup sequence. The duration of the R¯¯E¯S¯E¯T¯ low period after the startup sequence
has completed is governed by the RST_DUR register field described in Section 11.7.
24.2 HARDWARE RESET
A Hardware Reset is triggered when an external source pulls the R¯¯E¯S¯E¯T¯ pin low. Under this
condition, the WM8311 transitions to the OFF state. The contents of the Register map are cleared to
default values, except for the RTC and software scratch registers, which are maintained. The
WM8311 will then automatically schedule an ON state transition to resume normal operation.
If the external source continues to pull the R¯¯E¯S¯E¯T¯ pin low, then the WM8311 cannot fully complete
the ON state transition following the Hardware Reset. In this case, the WM8311 will mask the external
reset for up to 32 seconds. If the R¯¯E¯S¯E¯T¯ pin is released (ie. it returns to logic ‘1’) during this time,
then the ON state transition is completed and the Hardware Reset input is valid again from this point.
If the R¯¯E¯S¯E¯T¯ pin is not released, then the WM8311 will force an OFF condition on expiry of the 32
seconds timeout. Recovery from this forced OFF condition cannot occur until the external reset
condition is de-asserted, followed by a valid ON event. If an ON event occurs before the external
reset is de-asserted, then start-up will be attempted, but the transition will be unsuccessful, causing a
return to the OFF state.
It is possible to mask the R¯¯E¯S¯E¯T¯ pin input in the SLEEP state by setting the RST_SLP_MSK register
bit as described in Section 11.7.
24.3 SOFTWARE RESET
A Software Reset is triggered by writing to Register 0000h, as described in Section 12.5. In this event,
the WM8311 asserts the R¯¯E¯S¯E¯T¯ pin and transitions to the OFF state. If the Reset occurred in the ON
state, then the WM8311 will automatically return to the ON state following the Reset.
The SWRST_DLY register field determines whether a time delay is applied between the Software
Reset command and the resultant shutdown and start-up sequences. When the SWRST_DLY bit is
set, the programmable time delay PWRSTATE_DLY is applied before commencing the shutdown
sequence.
The timing of the Software Reset is illustrated in Figure 37. See Section 11.3 for a definition of the
PWRSTATE_DLY register.
The SW_RESET_CFG register field determines if the Register Map is reset under a Software Reset
condition.
Note that the SW_RESET_CFG control register is locked by the WM8311 User Key. This register can
only be changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
R16387
(4003h)
Power State
BIT
LABEL
9 SWRST_DLY
DEFAULT
0
R16390
(4006h)
Reset
Control
10 SW_RESET_C
1
FG
Table 107 Software Reset Configuration
DESCRIPTION
Software Reset Delay
0 = No delay
1 = Software Reset is delayed by
PWRSTATE_DLY following the Software
Reset command
Software Reset Configuration.
Selects whether the register map is reset to
default values when Software Reset occurs.
0 = All registers except RTC and Software
Scratch registers are reset by Software
Reset
1 = Register Map is not affected by Software
Reset
Protected by user key
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PP, May 2012, Rev 3.1
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