WM8311 Datasheet, PDF (147/302 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

Pre-Production
ADDRESS
BIT
(4042h)
LABEL
GPIO11
Control
R16451
(4043h)
3:0 GP12_FN [3:0]
GPIO12
Control
R16452
(4044h)
3:0 GP13_FN [3:0]
GPIO13
Control
R16453
(4045h)
3:0 GP14_FN [3:0]
GPIO14
Control
R16454
(4046h)
3:0 GP15_FN [3:0]
GPIO15
Control
R16455
(4047h)
3:0 GP16_FN [4:0]
GPIO16
Control
Table 82 GPIO Function Select Registers
WM8311
DEFAULT
0000
0000
DESCRIPTION
8h = DC1 DVS Done
9h = DC2 DVS Done
Ah = External Power Enable1
Bh = External Power Enable2
Ch = System Supply Good (SYSOK)
Dh = Converter Power Good
(PWR_GOOD)
Eh = External Power Clock (2MHz)
Fh = Auxiliary Reset
0000
0000
0000
Note that GPIO input functions 2h, 3h, 4h, 5h and 6h are edge-triggered only. The associated state
transition(s) are scheduled only when a rising or falling edge is detected on the respective GPIO pin.
At other times, it is possible that other state transition events may cause a state transition regardless
of the state of the GPIO input. See Section 11.3 for details of all the state transition events.
Note that SLEEP transitions are not possible when any of the Battery Charger Interrupts is set. If any
of the Battery Charger Interrupts is asserted when a SLEEP transition is requested, then the transition
will be unsuccessful and the WM8311 will remain in the ON power state. See Section 17.7.8 for
details of the Battery Charger Interrupts.
21.4 GPIO INTERRUPTS
Each GPIO pin has an associated interrupt flag, GPn_EINT, in Register R16405 (4015h). Each of
these secondary interrupts triggers a primary GPIO Interrupt, GP_INT (see Section 23). This can be
masked by setting the mask bit(s) as described in Table 83.
See Section 28 and Section 29 for a definition of the register bit positions applicable to each GPIO.
ADDRESS
BIT
LABEL
DESCRIPTION
R16405
(4015h)
Interrupt Status
5
15:0
GPn_EINT
GPIO interrupt.
(Trigger is controlled by GPn_INT_MODE)
Note: Cleared when a ‘1’ is written.
R16413
(401Dh)
15:0 IM_GPn_EINT
Interrupt Status
5 Mask
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Note: n is a number between 1 and 16 that identifies the individual GPIO.
Table 83 GPIO Interrupts
w
PP, May 2012, Rev 3.1
147