WM8777 Datasheet, PDF (43/102 Pages) Wolfson Microelectronics plc – 24 BIT 192KHZ AV RECEIVER ON A CHIP

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S/PDIF DATA/CLOCK RECOVERY
WM8777
The WM8777 uses a patented clock and data recovery scheme that allows an extremely low jitter
bandwidth on the output recovered clock. This is done by isolating the clock and data recovery
systems.
The data is recovered and stored in a buffer which modifies the frequency of the recovered clock via
a filter. This filter controls the jitter bandwidth using the register value FPLL.
SPDIF in
Data
recovery
Buffer
SPDIF out
Clock out
FPLL
Filter
Clock
recovery
Figure 24 S/PDIF Data and Clock Recovery System
The jitter bandwidth affects the rate at which the clock can change to track the incoming data rate,
resulting in a slower tracking time as FPLL is increased. Note that this effect is only apparent on
slowly changing input frequencies. Input signals that change frequency by a significant amount, i.e.
data rate changes, will cause the system to lose lock and to enter a quick tracking mode which will
open the filter bandwidth out to the maximum.
Table 30 lists the cut-off frequencies for the different values of FPLL.
REGISTER
ADDRESS
(42h)
S/PDIF
Data/Clock
Recovery
BIT LABEL
5:3 FPLL[2:0]
Table 30 PLL Frequency Ratio Control
DEFAULT DESCRIPTION
111
-3dB LPF Cut-Off
000 = Invalid
001 = 28.84Hz
010 = 14.92Hz
011 = 7.46Hz
100 = 3.73Hz
101 = 1.87Hz
110 = 0.97Hz
111 = 0.47Hz
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PP Rev 1.94 November 2004
43