WM8777 Datasheet, PDF (34/102 Pages) Wolfson Microelectronics plc – 24 BIT 192KHZ AV RECEIVER ON A CHIP

WM8777
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MASTER MODE REGISTERS
Control bit PAIFRX_MS selects between primary audio interface Master and Slave Modes. Control bit
SMS selects between secondary audio interface master and slave modes.
REGISTER BIT
ADDRESS
(19h)
7
Master Mode
Control
LABEL
PAIFTX_MS
8
PAIFRX_MS
(3Fh)
3
Secondary
Interface
Master Mode
Control
SMS
Table 23 Master Mode Registers
DEFAULT
DESCRIPTION
0
Master/Slave Interface mode select. If
ADCCLKSRC is set high then this register
control whether the ADC clocks are in
master or slave mode/
0 = Slave Mode – PDATAOPLRC and
ADCPBCLK are inputs
1 = Master Mode – PDATAOPLRC and
ADCPBCLK are outputs
0
Maser/Slave interface mode select
0 = Slave Mode – PDATAOPLRC,
PDATAIPLRC and PBCLK are inputs
1 = Master Mode – PDATAOPLRC,
PDATAIPLRC and PBCLK are outputs
Note if ADCCLKSRC is set high then this
register only controls PDATAIPLRC and
PBCLK.
0
Master/Slave interface mode select
0 = Slave Mode – SLRC and SPBCLK are
inputs
1 = Master Mode – SLRC and SPBCLK are
outputs
In Master mode the WM8777 generates PDATAOPLRC, PDATAIPLRC and PBCLK. These clocks
are derived from master clock and the ratio of MCLK to PDATAOPLRC and PDATAIPLRC are set by
PAIFTX_RATE, PAIFRX_RATE and SAIFRATE.
REGISTER ADDRESS BIT
LABEL
DEFAULT
(19h)
Master Mode Control
2:0
PAIFTX_RATE
[2:0]
010
6:4
PAIFRX_RATE
[2:0]
010
(3Fh)
Secondary Interface ^2:0
SAIFRATE
[2:0]
010
Master Mode Control
(3Fh)
5:4 SAIFCLKSRC[1:0]
00
Secondary Interface
Table 24 Master Mode MCLK:LRCLK Regsiters
DESCRIPTION
Master Mode MCLK:LRCLK
ratio select:
000 = 128fs
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
Audio interface master clock
source when SMS is 1.
00 = MCLK
01 = GPIO (If ADCCLKSRC
is set)
10 = PLL clock
11 = PLL clock
w
PP Rev 1.94 November 2004
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