WM8777 Datasheet, PDF (31/102 Pages) Wolfson Microelectronics plc – 24 BIT 192KHZ AV RECEIVER ON A CHIP

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WM8777
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25^oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
PBCLK cycle time
tBCY
PBCLK pulse width high
tBCH
PBCLK pulse width low
tBCL
PDATAIPLRC/PDATAOPL
RC set-up time to PBCLK
rising edge
tLRSU
PDATAIPLRC/PDATAOPL
tLRH
RC hold time from PBCLK
rising edge
PDATAIP1/2/3/4 set-up
tDS
time to PBCLK rising edge
PDATAIP1/2/3/4 hold time
tDH
from PBCLK rising edge
PDATAOP propagation
tDD
delay from PBCLK falling
edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
0
10
ns
Table 17 Digital Audio Data Timing – Slave Mode
Note: PDATAOPLRC and PDATAIPLRC should be synchronous with MCLK, although the WM8777 interface is tolerant of
phase variations or jitter on these signals.
The DACs support system clock to sampling clock ratios of 256fs to 1152fs when the DAC signal
processing of the WM8777 is programmed to operate at 128 times oversampling rate (DACOSR=0).
The DACs support ratios of 128fs and 192fs when the WM8777 is programmed to operate at 64
times oversampling rate (DACOSR=1).
The ADC supports system clock to sampling clock ratios of 128fs to 1152fs. The signal processing
for the WM8777 ADC typically operates at an oversampling rate of 128fs. For ADC operation at
96kHz in 256fs or 384fs mode it is recommended that the user set the ADCOSR bit. This changes
the ADC signal processing oversample rate from 128fs to 64fs. For ADC operation at 192kHz in
128fs or 192fs mode it is recommended that the user set the ADCOSR bit. This changes the ADC
signal processing oversample rate from 64fs to 32fs.
Table 18 shows the typical system clock frequencies for ADC operation at both 128 times
oversampling rate (ADCOSR=0) and 64 times oversampling rate (ADCOSR=1), and DAC operation
at 128 times oversampling rate (DACOSR=0). Table 19 shows typical system clock frequencies for
ADC operation at 32/64 times oversampling rate (ADCOSR=1), and DAC operation at 64 times
oversampling rate (DACOSR =1).
SAMPLING
RATE
(PDATAIPLRC/
PDATAOPLRC)
256fs
System Clock Frequency (MHz)
384fs
512fs
768fs
1152fs
32kHz
8.192 12.288
16.384
24.576
36.864
44.1kHz
11.2896 16.9340
22.5792
33.8688 Unavailable
48kHz
12.288 18.432
24.576
36.864 Unavailable
96kHz
24.576 36.864 Unavailable Unavailable Unavailable
Table 18 ADC and DAC system clock frequencies versus sampling rate. (ADC operation at
either 128 times oversampling rate (ADCOSR=0) or 64 times oversampling rate (ADCOSR=1),
DAC operation at 128 times oversampling rate, DACOSR=0)
w
PP Rev 1.94 November 2004
31