WM8326 Datasheet, PDF (36/255 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8326
Production Data
11.4 POWER STATE INTERRUPTS
Power State transitions are associated with a number of Interrupt event flags. Transitions to
BACKUP, SLEEP, ON or OFF states are indicated by the Interrupt bits described in Table 4. Each of
these secondary interrupts triggers a primary Power State Interrupt, PS_INT (see Section 23). This
can be masked by setting the mask bit(s) as described in Table 4.
ADDRESS
R16402
(4012h)
Interrupt Status
2
BIT
LABEL
2
PS_POR_EINT
1
PS_SLEEP_OFF_EINT
0
PS_ON_WAKE_EINT
R16410
(401Ah)
2
IM_PS_POR_EINT
Interrupt Status
2 Mask
1
IM_PS_SLEEP_OFF_EINT
0
IM_PS_ON_WAKE_EINT
Table 4 Power State Interrupts
DESCRIPTION
Power On Reset interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
SLEEP or OFF interrupt (Power state
transition to SLEEP or OFF states)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
ON or WAKE interrupt (Power state
transition to ON state)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
11.5 POWER STATE GPIO INDICATION
The WM8326 can be configured to generate logic signals via GPIO pins to indicate the current Power
State. See Section 21 for details of configuring GPIO pins.
A GPIO pin configured as “ON state” output will be asserted when the WM8326 is in the ON state.
A GPIO pin configured as “SLEEP state” output will be asserted when the WM8326 is in the SLEEP
state.
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PD, June 2012, Rev 4.0
36