WM8962 Datasheet, PDF (35/295 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8962
The P¯¯O¯R signal is undefined until AVDD has exceeded the minimum threshold, Vpora Once this
threshold has been exceeded, P¯¯O¯R is asserted low and the chip is held in reset. In this condition, all
writes to the control interface are ignored. Once AVDD and DCVDD have reached their respective
power on thresholds, P¯¯O¯R is released high, all registers are in their default state, and writes to the
control interface may take place.
A secondary reset circuit is associated with the PLLVDD supply. The PLLs are disabled and the
associated registers are undefined when PLLVDD is below its minimum threshold.
Note that a minimum power-on reset period, TPOR, applies even if AVDD and DCVDD have zero rise
time. (This specification is guaranteed by design rather than test.)
On power down, P¯¯O¯R is asserted low when any of AVDD or DCVDD falls below their respective
power-down thresholds.
Typical Power-On Reset parameters for the WM8962 are defined in Table 1.
SYMBOL
DESCRIPTION
Vpora
AVDD threshold below which POR is undefined
Vpora_on
Power-On threshold (AVDD)
Vpora_off
Vpord_on
Power-Off threshold (AVDD)
Power-On threshold (DCVDD)
Vpord_off
Vporp_on
Power-Off threshold (DCVDD)
PLL start-up threshold (PLLVDD)
Vporp_off
TPOR
PLL reset threshold (PLLVDD)
Minimum Power-On Reset period
Table 1 Typical Power-On Reset Parameters
TYP
0.5
1.1
1.1
0.9
0.65
1.1
1.1
9.5
UNIT
V
V
V
V
V
V
V
s
Notes:
1. If AVDD and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating
level but do not go below Vpora_off or Vpord_off) then the chip does not reset and resumes normal
operation when the voltage is back to the recommended level again.
2. The chip enters reset at power down when AVDD or DCVDD falls below Vpora_off or Vpord_off. This
may be important if the supply is turned on and off frequently by a power management system.
3. The minimum TPOR period is maintained even if DCVDD and AVDD have zero rise time. This
specification is guaranteed by design rather than test.
4. The WM8962 can operate with PLLVDD tied to 0V, but the crystal oscillator, PLLs and CLKOUT
functions will not be supported.
Rev 4.3
35