WM8962 Datasheet, PDF (168/295 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8962
FREE-RUNNING FLL CLOCK
The Frequency Locked Loop (FLL) can generate a clock signal even when no external reference is
available. However, it should be noted that the accuracy of this clock is reduced, and an external
reference source should always be used where possible. Note that, in free-running modes, the FLL is
not sufficiently accurate for hi-fi ADC or DAC applications. However, the free-running modes are
suitable for clocking most other functions, including the Write Sequencer, Charge Pump, DC Servo
and Class D loudspeaker driver. Note that the free-running FLL mode enables microphone/accessory
detection interrupts to be supported without external clocking.
If an accurate reference clock is initially available, then the FLL should be configured as described
above. The FLL will continue to generate a stable output clock after the reference input is stopped or
disconnected.
If no reference clock is available at the time of starting up the FLL, then an internal clock frequency of
approximately 12MHz can be generated by implementing the following sequence:
 Enable the FLL Analogue Oscillator (FLL_OSC_ENA = 1)
 Set the FOUT clock divider to divide by 8 (FLL_OUTDIV = 000111)
 Configure the oscillator frequency by setting FLL_FRC_NCO = 1 and FLL_FRC_NCO_VAL =
19h
Note that the free-running FLL mode is not suitable for hi-fi CODEC applications. In the absence of
any reference clock, the FLL output is subject to a very wide tolerance; see “Electrical Characteristics”
for details of the FLL accuracy.
Note that the free-running FLL clock is selected as SYSCLK using the registers noted in Figure 58.
The free-running FLL clock may be used to support analogue functions, for which the digital audio
interface is not used, and there is no applicable Sample Rate (fs). When SYSCLK is required for
circuits such the Class D, DC Servo, Control Write Sequencer or Charge Pump, then valid Sample
Rate register settings (SAMPLE_RATE and MCLK_RATE) are still required, even though the digital
audio interface is not active.
REGISTER BIT
ADDRESS
LABEL
R155 (009Bh) 1 FLL_OSC_ENA
FLL Control
(1)
R159 (009Fh) 6:1 FLL_FRC_NCO
FLL Control
_VAL
(5)
0 FLL_FRC_NCO
Table 113 FLL Free-Running Mode
DEFAULT
DESCRIPTION
0
FLL Oscillator enable
0 = Disabled
1 = Enabled
(Note that this field is required for free-
running FLL modes only)
19h
FLL Forced oscillator value
Valid range is 000000 to 111111
0x19h (011001) = 12MHz approx
(Note that this field is required for free-
running FLL modes only)
0
FLL Forced control select
0 = Normal
1 = FLL oscillator controlled by
FLL_FRC_NCO_VAL
(Note that this field is required for free-
running FLL modes only)
168
Rev 4.3