WM8962 Datasheet, PDF (173/295 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8962
The PLL Control registers are described in Table 118. Example PLL calculations are shown on the
following page, suitable for generating 12MHz or 24.576MHz clocks from the 24MHz reference.
REGISTER
ADDRESS
R125 (7Dh)
Analogue
Clocking 2
BIT
7
6
LABEL
PLL2_OUTDIV
PLL3_OUTDIV
R136 (88h) 6
PLL 9
PLL2_FRAC
4:0
PLL2_N [4:0]
R137 (89h) 7:0
PLL 10
R138 (8Ah) 7:0
PLL 11
R139 (8Bh) 7:0
PLL 12
R140 (8Ch) 6
PLL 13
PLL2_K [23:16]
PLL2_K [15:8]
PLL2_K [7:0]
PLL3_FRAC
4:0
PLL3_N [4:0]
R141 (8Dh) 7:0
PLL 14
PLL3_K [23:16]
R142 (8Eh) 7:0
PLL 15
PLL3_K [15:8]
R143 (8Fh) 7:0
PLL 16
PLL3_K [7:0]
Table 118 PLL Frequency Ratio Control
DEFAULT
DESCRIPTION
0
1
1
0_0111
1Ch
71h
PLL2 Output Divider
0 = Divide by 2
1 = Divide by 4
PLL3 Output Divider
0 = Divide by 2
1 = Divide by 4
PLL2 Fractional enable
0 = Integer Mode
1 = Fractional Mode (recommended)
Integer Multiply for PLL2
(LSB = 1)
Fractional Multiply for PLL2
(MSB = 0.5)
C7h
1
0_0111
48h
22h
PLL3 Fractional enable
0 = Integer Mode
1 = Fractional Mode (recommended)
Integer Multiply for PLL3
(LSB = 1)
Fractional Multiply for PLL3
(MSB = 0.5)
97h
Rev 4.3
173