WM8983_06 Datasheet, PDF (18/123 Pages) Wolfson Microelectronics plc – Mobile Multimedia CODEC with 1W Speaker Driver

WM8983
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK
t_MCLKL
t_MCLKH
t_MCLKY
Production Data
Figure 5 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA = +25^oC, Slave Mode
PARAMETER
System Clock Timing Information
MCLK cycle time
MCLK duty cycle
Note:
SYMBOL
CONDITIONS
MIN
TMCLKY
TMCLKDS
MCLK=SYSCLK (=256fs)
MCLK input to PLL ^{Note 1}
81.38
20
60:40
TYP
MAX
40:60
UNIT
ns
ns
1. PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
AUDIO INTERFACE TIMING – MASTER MODE
Figure 6 Digital Audio Data Timing – Master Mode (see Control Interface)
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PD Rev 4.0 November 2006
18