WM8718 Datasheet, PDF (14/27 Pages) Wolfson Microelectronics plc – 24 BIT DIFFERENTIAL STEREO DAC WITH VOLUME CONTROL

WM8718
Production Data
REGISTER MAP
WM8718 uses a total of 4 program registers, which are 16-bits long. These registers are all
loaded through input pin SDIN, using the 3-wire serial control mode as shown in 9.
A6 A5 A4 A3 A2 A1 A0 D8
D7
D6
M0 0
0
0
0
0
0
0 UPDATEL LAT7
LAT6
M1 0
0
0
0
0
0
1 UPDATER RAT7
RAT6
M2 0
0
0
0
0
1
0 ZCDINIT ZEROFLR
0¹
M3 0
0
0
0
0
1
1
0¹
REV
BCP
ADDRESS
D5
D4
LAT5
LAT4
RAT5
0¹
RAT4
0¹
ATC
LRP
DATA
D3
D2 D1 D0
LAT3
LAT2 LAT1 LAT0
RAT3
0¹
RAT2 RAT1 RAT0
PWDN DEEMPH MUT
FMT[1] FMT[0] IWL[1] IWL[0]
Table 2 Mapping of Program Registers
Note:
1. These register bits must be written as 0 otherwise device function can not be guaranteed.
REGISTER
ADDRESS
(A3,A2,A1,A0)
0000
DACL
Attenuation
0001
DACR
Attenuation
0010
Mode Control
0011
Format
Control
BITS
[7:0]
8
[7:0]
8
0
1
2
7
8
[1:0]
NAME
DEFAULT DESCRIPTION
LAT[7:0]
UPDATEL
RAT[7:0]
UPDATER
MUT
DEEMPH
PWDN
ZEROFLR
ZCDINIT
IWL[1:0]
11111111 (0dB)
0
11111111 (0dB)
0
0
0
0
0
0
10
Attenuation data for left channel in 0.5dB steps, see Table 5
Attenuation data load control for left channel.
0: Store DACL in intermediate latch (no change to output)
1: Store DACL and update attenuation on both channels.
Attenuation data for right channel in 0.5dB steps, see Table 5
Attenuation data load control for right channel.
0: Store DACR in intermediate latch (no change to output)
1: Store DACR and update attenuation on both channels.
Left and Right DACs Soft Mute Control.
0: No mute
1: Mute
De-emphasis Control.
0: De-emphasis off
1: De-emphasis on
Left and Right DACs Power-down Control
0: All DACs running, output is active
1: All DACs in power saving mode, output muted
Zero Flag Pin Control.
0: Channel independent
1: AND of both channels on ZEROFL output pin
Zero Cross Detect Control.
0: Zero cross detect enabled
1: Zero cross detect disabled
Input Word Length.
00: 16-bit mode
01: 20-bit mode
10: 24-bit mode
11: 32-bit mode(not supported in right justified mode)
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PD Rev 4.1 March 2004
14