WM8718 Datasheet, PDF (11/27 Pages) Wolfson Microelectronics plc – 24 BIT DIFFERENTIAL STEREO DAC WITH VOLUME CONTROL

WM8718
Production Data
The WM8718 will automatically detect when data with a LRCIN period of exactly 32 BCKINs is
sent, and select 16-bit mode - overriding any previously programmed word length. Word length
will revert to a programmed value only if a LRCIN period other than 32 BCKINs is detected.
In DSP early or DSP late mode, the data is time multiplexed onto DIN. LRCIN is used as a frame
sync signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN
period is 2 times the selected word length. Any mark to space ratio is acceptable on LRCIN
provided the rising edge is correctly positioned. (See Figure 7 and Figure 8)
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
LRCIN
BCKIN
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DIN
123
MSB
n-2 n-1 n
LSB
123
MSB
n-2 n-1 n
LSB
Figure 4 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
LRCIN
BCKIN
LEFT CHANNEL
1/fs
RIGHT CHANNEL
DIN
123
n-2 n-1 n
123
n-2 n-1 n
MSB
LSB
MSB
LSB
Figure 5 Right Justified Mode Timing Diagram
I²S MODE
In I²S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left data word and high during the right data word.
1/fs
LRCIN
LEFT CHANNEL
RIGHT CHANNEL
BCKIN
1 BCKIN
DIN
123
MSB
n-2 n-1 n
LSB
Figure 6 I²S Mode Timing Diagram
w
1 BCKIN
123
MSB
n-2 n-1 n
LSB
PD Rev 4.1 March 2004
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