74HC595 Datasheet, PDF (4/8 Pages) NXP Semiconductors – 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

WS74HC595
DC ELECTRICAL CHARACTERISTICS
(Apply across temperature range unless otherwise specified)
PARAMETER
VOH
VOL
II
IOZ
Icc
Ci
TA = 25℃
54HC595
TEST CONDITIONS
Vcc MIN TYP MAX MIN
2 V 1.9 1.998
1.9
IOH = -20uA 4.5V
4.4 4.499
4.4
VI= VIH or VIL
6 V 5.9 5.999
5.9
IOH = -6 mA 4.5V
3.98 4.3
3.84
IOH = -7.8mA 6 V 5.48 5.8
5.34
2V
0.002 0.1
IOL =20uA 4.5V
0.001 0.1
VI= VIH or VIL
6V
0.001 0.1
IOL = 6mA 4.5V
0.17 0.26
IOL =7.8mA 6 V
0.15 0.26
VI = Vcc or 0
6V
±0.1 ±100
VO = Vcc or 0, Q1-Q8
6V
±0.01 ±0.5
VI = Vcc or 0 IO = 0
6V
8
2V ~ 6V
3
10
74HC595
MAX UNIT
V
0.1
0.1
0.1 _V
0.33
0.33
±1000 nA
±5 uA
80 _uA
10 pF
TIMING REQUREMENTS OVER RECOMMENED OPERATING FREE-AIR TEMPERATURE
RANGE (unless otherwise noted)
Parameter
Symbol Unit Guaranteed Limit
Test Condition
Clock frequency
Pulse duration
Setup time
Hold time,
TA=25℃
fclock MHz
6
31
36
tw
ns
80
16
14
80
16
14
100
20
17
75
15
tsu
ns
13
50
10
9
50
10
9
th
ns
0
-40~+85
5
25
29
100
20
17
100
20
17
125
25
21
94
19
16
65
13
11
60
12
11
0
Vcc=2.0V
Vcc=4.5V
Vcc=6.0V
Vcc=2.0V SRCK or LCK high or low
Vcc=4.5V
Vcc=6.0V
Vcc=2.0V SRCL low
Vcc=4.5V
Vcc=6.0V
Vcc=2.0V
Vcc=4.5V SER before SRCK↑
Vcc=6.0V
Vcc=2.0V
Vcc=4.5V
Vcc=6.0V
SRCK↑ before LCK↑
(Note 4)
Vcc=2.0V
Vcc=4.5V SRCL low before RCK↑
Vcc=6.0V
Vcc=2.0V
Vcc=4.5V
Vcc=6.0V
Vcc=2~6V
SRCL high(inactive)
before SRCK↑
SER after SRCK↑
Note: . 4. This setup time allows the latch to receive stable data from the shift register. The clock can
be connected together, in this case the shift register is one clock pulse ahead of the latch.
4