74HC595 Datasheet, PDF (2/8 Pages) NXP Semiconductors – 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

FUNCTIONAL DESCRIPTION
WS74HC595
1. Truth Table
Inputs
Function
SER SRCK SRCL RCK OE
X
X
X
X
H Outputs Q1-Q8 are disabled.
X
X
X
X
L
Outputs Q1-Q8 are enabled.
X
X
L
X
X Shift register is cleared.
L
↑
H
X
X First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X
X
X
↑
X
Shift-register data is stored in the latch.
H = High Level (steady state). L= Low Level (steady state)
X = Irrelevant (don’t care)
↑= Transition from low to high level.
2. Logic Waveform
SRCK
SER
RCK
SRCL
OE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q8'
Note:
implies that the outputs are in 3-state mode.
2