W83194BR-730 Datasheet, PDF (9/14 Pages) Winbond – 166MHZ CLOCK FOR SIS CHIPSET

W83194BR-730
PRELIMINARY
5.4 Register 3: SDRAM Clock Additional Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
1
33 SDRAM7 (Active / Inactive)
6
1
34 SDRAM6 (Active / Inactive)
5
1
36 SDRAM5 (Active / Inactive)
4
1
37 SDRAM4 (Active / Inactive)
3
1
38 SDRAM3 (Active / Inactive)
2
1
40 SDRAM2 (Active / Inactive)
1
1
41 SDRAM1 (Active / Inactive)
0
1
42 SDRAM0 (Active / Inactive)
5.5 Register 4: SDRAM Clock Additional Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
X
- AGPSEL#
6
X
- FS3#
5
X
- FS2#
4
X
- FS1#
3
X
- FS0#
2
1
28 SDRAM10 (Active / Inactive)
1
1
30 SDRAM9 (Active / Inactive)
0
1
31 SDRAM8 (Active / Inactive)
5.6 Register 5: Skew Register
Bit @PowerUp Pin
Description
7
1
- CSkew2 (SDRAM to CPU skew program bit)
6
0
- CSkew1 (SDRAM to CPU skew program bit)
5
0
- CSkew0 (SDRAM to CPU skew program bit)
4
1
- CAkew2 (AGP to CPU skew program bit)
3
0
- CAkew1 (AGP to CPU skew program bit)
2
0
- CAkew0 (AGP to CPU skew program bit)
1
1
21 24_48MHz(Active / Inactive)
0
1
20 48MHz(Active / Inactive)
Publication Release Date:Oct. 2000
-9-
Revision 0.60