W83194BR-730 Datasheet, PDF (4/14 Pages) Winbond – 166MHZ CLOCK FOR SIS CHIPSET

W83194BR-730
4.3 I²C Control Interface
SYMBOL
PIN
SDATA*
23
SDCLK*
24
PRELIMINARY
I/O
FUNCTION
I/O Serial data of I²C 2-wire control interface
IN Serial clock of I²C 2-wire control interface
4.4 Fixed Frequency Outputs
SYMBOL
PIN
REF0 ^/ &AGPSEL
2
REF1 ^/ &FS3
3
24_48MHz / &Mode
21
48MHz / &FS0
20
I/O
FUNCTION
I/O 14.318MHz reference clock. This REF output is the
atched input for &AGPSEL at initial power up for H/W
selecting the output frequency of AGP clocks.
I/O 14.318MHz reference clock.
Latched input for FS3 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
I/O 24_48MHz output clock, selected by pin16.
Latched Input. &Mode=0, Pin 27,28,30,31 are SDRAM
clocks; &Mode=0, Pin27,28,29,31 areCPU_STOP#,
SDRAM_STOP#, PCI_STOP#,PD#
I/O 48MHz output for USB during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
4.5 Power Pins
SYMBOL
VddR
VddAGP
VddLCPU
VddP
VddSD
Vdd48
Vss
PIN
FUNCTION
1
Power supply for Ref [0:1] crystal and core logic.
15
Power supply for AGP output, 3.3V.
48
Power supply for CPUC0,T0,CS_C1, either 2.5V or 3.3V.
7
Power supply for PCICLK[0:5], 3.3V.
43,35,29,25
Power supply for SDRAM[0:12], and CPU PLL core,
nominal 3.3V.
19
Power for 24 & 48MHz output buffers and fixed PLL core.
4,14,18,19,29,32,39,4 Circuit Ground.
4
Publication Release Date:Oct. 2000
-4-
Revision 0.60