W83194BR-730 Datasheet, PDF (8/14 Pages) Winbond – 166MHZ CLOCK FOR SIS CHIPSET

W83194BR-730
PRELIMINARY
5.1 Register 0: Frequency Select Register
Bit @PowerUp
Pin
Description
7
0
6
0
5
0
4
0
3
0
2
0
-
SSEL5 ( Frequency table selection by software via I²C)
-
SSEL4 ( Frequency table selection by software via I²C)
-
SSEL3 ( Frequency table selection by software via I²C)
-
SSEL2 ( Frequency table selection by software via I²C)
-
SSEL1 ( Frequency table selection by software via I²C)
-
SSEL0 (Frequency table selection by software via I²C )
1
0
-
0 = Selection by hardware
1 = Selection by software I²C - Bit (7:2)
0
0
-
0 = Running
1 = Tristate all outputs
5.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
1
- CPUCS_C1$ free running control 1: stopped by CPU_STOP#
0: Free running pin
6
1
27 SDRAM11 (Active / Inactive)
5
0
- 0 = Normal
1 = Spread spectrum enable
4
0
- 0 = ±0.25% Center type Spread Spectrum Modulation
1= 0 ~ (-0.5%) Down type Spread Spectrum Modulation
3
1
26 SDRAM12 (Active / Inactive)
2
1
45 CPUCS_C1$(Active / Inactive)
1
1
46 CPUC0$ (Active / Inactive)
0
1
47 CPUT0$ (Active / Inactive)
5.3 Register 2: PCI, AGP Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
1
17 AGPCLK1(Active / Inactive)
6
1
16 AGPCLK0(Active / Inactive)
5
1
13 PCICLK5 (Active / Inactive)
4
1
12 PCICLK4 (Active / Inactive)
3
1
11 PCICLK3 (Active / Inactive)
2
1
10 PCICLK2 (Active / Inactive)
1
1
9 PCICLK1 (Active / Inactive)
0
1
8 PCICLK0 (Active / Inactive)
Publication Release Date:Oct. 2000
-8-
Revision 0.60