W78958B Datasheet, PDF (9/28 Pages) Winbond – 8-BIT EMULATION MICROCONTROLLER

W78958B
P8.7−P8.0 Port 8, Bits 7−0, Input/Output
TYPE
MODE
DESCRIPTION
Advanced
Standard
Normal
Emulation
Normal
Functions are the same as those of Port 1 in the W78C31, except
that they are mapped by the P8 register and not bit-addressable. The
P8 register is not a standard register in the W78C32. Its address is at
0A6H.
Frozen in the original state.
P8.1 (ROMS1, standard type ROM size Select 1) and P8.0 (ROMS0)
are the input pins that determine which of four different ROM sizes is
being used: 4K, 8K, 16K, or 32K bytes. For details, see Table D1−
D4.
Emulation Frozen in the original state.
INT2 and INT3 External Interrupt 2 and 3, Input
TYPE
Advanced
Standard
MODE
Normal
Emulation
-
DESCRIPTION
Functions are similar to those of external interrupt 0 and 1 in the
W78C31, except that the functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt
Control) register. For details, see Table D6. The XICON register is
bit-addressable but is not a standard register in the W78C32. Its
address is at 0C0H. The interrupt vector addresses and the priority
polling sequence within the same level are shown in Table D7.
Frozen in the original state.
Not supported.
BIT ADDR.
7 0C7H
6 0C6H
5 0C5H
4 0C4H
3 0C3H
2 0C2H
1 0C1H
0 0C0H
NAME
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
FUNCTION
High/low priority level for INT 3 is specified when this bit is
set/cleared by software.
Enable/disable interrupt from INT3 when this bit is set/cleared by
software.
If IT3 is "1," IE3 is set/cleared automatically by hardware when
interrupt is detected/serviced.
INT3 is falling-edge/low-level triggered when this bit is set/cleared by
software.
High/low priority level for INT 2 is specified when this bit is
set/cleared by software.
Enable/disable interrupt from INT 2 when this bit is set/cleared by
software.
If IT2 is "1," IE2 is set/cleared automatically by hardware when
interrupt is de0tected/serviced.
INT 2 is falling-edge/low-level triggered when this bit is set/cleared
by software.
Table D6. Functions of XICON Register.
Publication Release Date: September 1997
-9-
Revision A3