W78958B Datasheet, PDF (13/28 Pages) Winbond – 8-BIT EMULATION MICROCONTROLLER

W78958B
byte address is no longer needed in this type. The advanced type supports 64 KB of external program
memory and 64 KB of external data memory, just as a W78C32 does.
The programming of the advanced type is fully compatible with that of the W78C32 except that the
external data RAM is accessed by a "MOVX @Ri" instruction. To support address paging, there is an
additional 8-bit SFR "HB" (high byte), which is a nonstandard register, at address 0A1H. During the
execution of "MOVX @Ri," the contents of HB are output to AP6. The page address is modified by
loading the HB register with a new value before execution of the "MOVX @Ri" instruction. To
read/write the HB register, one can use the "MOV direct" instruction or "read-modify-write"
instructions. The HB register does not support bit-addressable instructions.
The advanced type provides four pins, AP7.3−AP7.0 (CS3−CS0), to support either 1 MB
program/data memory space or memory-mapped chip select logic. Bit 7 of EPMA (Extended Program
Memory Address) register determines the functions of these pins. When this bit is "0" (default value),
AP7<3:0> support external program and data memory addresses up to 1 MB for applications that
require additional external memory to store large amounts of data. During the execution of "MOVC
A,@A+DPTR" to read the external ROM data, the execution of "MOVX @DPTR,A" to write the
external RAM data, or the execution of "MOVX A,@DPTR" to read the external RAM data, AP7<3:0>
output address <19:16> from bits <3:0> of the EPMA (Extended Program Memory Address) register.
Excluding that time, AP7<3:0> always output 0H to ensure the instruction fetch is within the 64K
program memory address. Different banks can be selected by modifying the content of the EPMA
register before the execution of these instructions.
When EPMA.7 is "1," AP7<3:0> are output pins that support the memory-mapped peripheral chip
select logic, which eliminates the need for glue logic. These pins are decoded by AP6<7:6>. Only one
of the pins is active low at any one time. That is, they are active individually with 16 K address
resolution. For example, CS0 is active low for the address range from 0000H to 3FFFH, CS1 is active
low for 4000H to 7FFFH, and so forth.
The EPMA register is a nonstandard 8-bit SFR at address 0A2H in the W78C32. To read/write the
EPMA register, one can use the "MOV direct" instruction or "read-modify-write" instructions. Bits
<6:4> of the EPMA register are reserved bits, and their output values are 111B if they are read. The
content of EPMA is 70H after RESET. The EPMA register does not support bit-addressable
instructions.
The advanced type provides one parallel I/O port, Port 8. Its function is the same as that of Port 1 in
the W78C31, except that the port is mapped by the P8 register and is not bit-addressable. The P8
register is not a standard register in the W78C32. Its address is at 0A6H. To read/write the P8
register, one can use the "MOV direct" instruction or "read-modify-write" instructions.
The advanced type provides two additional external interrupts, INT 2 and INT 3 , whose functions are
similar to those of external interrupt 0 and 1 in the W78C31. The functions/status of these interrupts
are determined/shown by the bits in the XICON (External Interrupt Control) register. For details, see
Table D6. The XICON register is bit-addressable but is not a standard register in the W78C32. Its
address is at 0C0H. To set/clear the bits of the XICON register, one can use the "SETB (or CLR) bit"
instruction. For example, "SETB 0C2H" sets bit EX2 of XICON. The interrupt vector addresses and
the priority polling sequence within the same level are shown in Table D7.
For a description of the emulation functions of the advanced type, refer to the section below on the
emulation functions.
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Publication Release Date: September 1997
Revision A3