ISD2560 Datasheet, PDF (9/42 Pages) Winbond – ISD2560

ISD2560/75/90/120
PIN NAME
XCLK
P/ R
PIN NO.
SOIC/ TSOP
PDIP
26
5
27
6
FUNCTION
External Clock: The external clock input has an internal pull-down
device. The device is configured at the factory with an internal
sampling clock frequency centered to ±1 percent of specification.
The frequency is then maintained to a variation of ±2.25 percent
over the entire commercial temperature and operating voltage
ranges. If greater precision is required, the device can be clocked
through the XCLK pin as follows:
Part Number
Sample Rate
Required Clock
ISD2560
8.0 kHz
1024 kHz
ISD2575
6.4 kHz
819.2 kHz
ISD2590
5.3 kHz
682.7 kHz
ISD25120
4.0 kHz
512 kHz
These recommended clock rates should not be varied because the
antialiasing and smoothing filters are fixed, and aliasing problems
can occur if the sample rate differs from the one recommended.
The duty cycle on the input clock is not critical, as the clock is
immediately divided by two. If the XCLK is not used, this input
must be connected to ground.
Playback/Record: The P/ R input pin is latched by the falling edge
of the CE pin. A HIGH level selects a playback cycle while a LOW
level selects a record cycle. For a record cycle, the address pins
provide the starting address and recording continues until PD or
CE is pulled HIGH or an overflow is detected (i.e. the chip is full).
When a record cycle is terminated by pulling PD or CE HIGH,
then End-Of-Message ( EOM ) marker is stored at the current
address in memory. For a playback cycle, the address inputs
provide the starting address and the device will play until an EOM
marker is encountered. The device can continue to pass an EOM
marker if CE is held LOW in address mode, or in an Operational
Mode. (See Operational Modes section)
Publication Release Date: May 2003
-9-
Revision 1.0