W83176R-735 Datasheet, PDF (8/11 Pages) Winbond – 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

W83176R-735
8. SPECIFICATIONS
8.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs
must always be tied to an appropriate logic voltage level (Ground or VDD).
SYMBOL
VDD, AVDD
T_STG
T_B
T_A
PARAMETER
Voltage on any pin with respect to GND
Storage Temperature
Ambient Temperature
Operating Temperature
RATING
-0.5V to +3.6V
-65°C to +150°C
-55°C to +125°C
0°C to +70°C
8.2 A.C. Characteristics
VDD = AVDD = 2.5V ±5 %, TA = 0°C to +70°C, Test load = 10 pF
PARAMETER
Operating Clock
Frequency
Input Clock Duty Cycle
Dynamic Supply Current
Cycle to Cycle Jitter
Output to Output Skew
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Output Differential-pair
Crossing Voltage
SYM. MIN. TYP.
FIN
100
Dtin
Idd
C-
Cjitter
Tskew
Tor
Tof
Dtot
Voc
40
650
650
45
(VDD/2)
-0.2
VDD/
2
MAX.
200
60
300
200
100
950
950
55
(VDD/2)
+ 0.2
UNITS
MHz
%
mA
pS
pS
pS
pS
%
V
TEST CONDITIONS
Fin =100 to 200 MHz
Fout =100 to 200 MHz
Fout =100 to 200 MHz
Fout =100 to 200 MHz
Fout =100 to 200 MHz
Fout =100 to 200 MHz
Fout =100 to 200 MHz
8.3 D.C. Characteristics
VDD = AVDD = 2.5V ±5%, TA = 0°C to +70°C
PARAMETER
SYM.
SDATA, SCLK Input Low Voltage
SDATA, SCLK Input High Voltage
CLKIN, FBIN Input Voltage Low
CLKIN, FBIN Input Voltage High
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
SV_IL
SV_IH
V_IL
V_IH
C_IN
C_OUT
L_IN
9. ORDERING INFORMATION
MIN.
2.2
2.1
TYP.
MAX.
1.0
0.4
5
6
7
UNITS
Vdc
TEST CONDITIONS
V_dc
V_dc Fin = 100 to 200 MHz
V_dc Fin = 100 to 200 MHz
pF
pF
nH
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