W83176R-735 Datasheet, PDF (3/11 Pages) Winbond – 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

W83176R-735
1. GENERAL DESCRIPTION
The W83176R-735 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS system. W83176R-735
can support 3 D.D.R. DRAM DIMMs.
The W83176R-735 provides I²C serial bus interface to program the registers to enable or disable each
clock outputs. The W83176R-735 accepts a reference clock as its input and runs on 2.5V supply.
2. FEATURES
• Zero-delay clock outputs
• Feedback pins for synchronous
• Supports up to 3 D.D.R. DIMMs
• One pairs of additional outputs for feedback
• Low Skew outputs (<100 pS)
• Supports 400 MHz D.D.R. SDRAM
• I²C 2-Wire serial interface and supports Byte or Block Date RW
• Packaged in 48-pin SSOP
3. PIN CONFIGURATION
GND 1
CLKC0 2
CLKT0 3
VDD 4
CLKT1 5
CLKC1 6
GND 7
GND 8
CLKC2 9
CLKT2 10
VDD 11
* SCLK 12
CLK_INT 13
N/C 14
VDD 15
AVDD 16
AGND 17
GND 18
CLKC3 19
CLKT3 20
VDD 21
CLKT4 22
CLKC4 23
GND 24
*: Internal pull-up resistor 120K to VDD
48 GND
47 CLKC5
46 CLKT5
45 VDD
44 CLKT6
43 CLKC6
42 GND
41 GND
40 CLKC7
39 CLKT7
38 VDD
37 SDATA *
36 N/C
35 FB_INT
34 VDD
33 FB_OUTT
32 NC
31 GND
30 CLKC8
29 CLKT8
28 VDD
27 CLKT9
26 CLKC9
25 GND
Publication Release Date: April 13, 2005
-1-
Revision 1.1